28,973 technical terms and definitions
peri gate spacer, source drain extension offset, anisotropic gate spacer, hv lv spacer width
Gate spacer etch is the step that decides exactly how close a source/drain implant can get to a peripheral transistor's channel, and it does that job the same way slit-spacer etch…
joint etch 3d nand, sac poly recess, lower deck upper deck alignment, channel hole deck seam etch, multi deck channel hole
Inter-deck plug, or joint etch, is the step that exists purely to let a channel hole be cut in two separate passes and still come out looking like one continuous hole — a seam…
word line deck bonding, cba cell array bonding, nand cell density increase, xtacking 3d nand
3D NAND String Architecture Beyond 200 Layers is a vertical stacking technology enabling unprecedented cell densities through 200+ controllable word line layers, mechanical…
peri ct etch, peri mc contact, peripheral logic deep via, periphery oxide fill contact
Peripheral deep contact, or Peri CT (sometimes Peri MC), reaches peripheral logic the same way TAC reaches the periphery underneath the array — a single deep via through a lot…
peri gate etch, poly gate etch dual oxide, hv lv gate oxide etch, gate oxide thickness selectivity
Peripheral gate etch cuts the HV and LV poly gates that make the periphery's two different transistor types work, and it has to do it as a single pass over a surface that is…
peri sti etch, shallow trench isolation 3d nand, hv lv transistor isolation, sti recess peripheral logic
Peripheral STI etch is the very first etch in the entire 3D NAND flow, and it looks nothing like any of the array-side etches that follow it — because it runs before the array…
sin pull back etch, word line metal recess, tungsten etch back 3d nand, molybdenum word line etch, csl contact fill, gate replacement module
Replacement gate is the step where 3D NAND actually becomes a gate-all-around transistor array, and it runs entirely through the slit trench that was just cut: every sacrificial…
slit bottom open etch, source line plate exposure etch, gls bottom punch, slit punch selectivity etch
Slit bottom punch is a short, separate etch run right after the main slit cut, and it exists because stopping a deep trench etch exactly on a thin film is a different, harder…
gate line slit etch, gls etch 3d nand, sub block slit cut, tsg ssl cut drain select, bsg gsl cut source select, slit bottom punch
Slit etch, usually called gate-line slit or GLS, is the long trench that turns one continuous ONON stack into separate, electrically isolated memory blocks — and it is also…
anisotropic slit spacer, slit sidewall insulation etch, slit floor clear etch, csl isolation spacer
Slit-spacer etch has one very specific job: remove an insulating film from the floor of the slit while leaving it fully intact on the walls, so the trench can be filled without…
side wall ono removal, swc etch 3d nand, sacrificial source poly strip, source poly recess, lateral channel source connection
Source formation is the etch family that reaches the channel from a direction nothing else in the flow uses: sideways, through the slit, rather than straight down through…
staircase trim etch, stair etch 3d nand, word line contact landing, chop etch split zone staircase, staircase oxide recess
3D NAND staircase etch spends more process time than almost any other single etch module in the flow, because every one of the 200 to 300-plus word lines buried in the ONON film…
step etch 3d nand, staircase pad exposure etch, sin landing pad etch, staircase oxide recess sequence
Step etch is easy to confuse with the trim-etch loop that shapes the staircase, but it is a separate etch with a separate job: once the staircase's shape is fully cut, step etch…
string select transistor gidl, nand read disturb leakage, ssl gsl leakage nand
3D NAND String Current Leakage A 3D NAND string packs dozens to hundreds of memory cells in series along a single vertical channel, and reading any one of them means passing…
3d nand string current uniformity prediction, 3d nand string, nand string current, string current uniformity, current uniformity prediction, 3d nand, nand string, string current
3D NAND String Current Uniformity Prediction with Machine Learning Introduction & Motivation 3D NAND String Current Uniformity Prediction with Machine Learning addresses a central…
tac etch, tav etch 3d nand, through array via, cmos under array contact, dummy oxide region etch
Through-array contact etch, TAC or TAV, is the one etch in the entire 3D NAND flow that deliberately avoids every structure the rest of the process just spent dozens of modules…
tsc etch, backside via etch bonded nand, xtacking through silicon contact, bonded wafer backside routing
Through-silicon contact, or TSC, is an etch that simply does not exist in a CMOS-under-array chip, because it only becomes necessary once a design has already bonded two separate…
tsg cut etch, ssl cut etch, string select line cut, drain side select gate isolation, top select gate etch
TSG/SSL cut is the shallowest trench etch anywhere in the 3D NAND array, and its entire job is splitting one continuous drain-side select-gate layer into independently switchable…
predicting vertical string uniformity in 3d nand architecture, predicting vertical string, vertical string uniformity, string uniformity 3d, uniformity 3d nand, 3d nand architecture
Predicting vertical string uniformity in 3D NAND architecture Introduction & Motivation Predicting vertical string uniformity in 3D NAND architecture addresses a central problem…
wlc etch, staircase contact etch, contact to control gate cc, multi depth contact etch, selective contact landing etch
Word-line contact etch is the step that finally reaches every one of the 200 to 300-plus word lines the replacement-gate module just finished building, and it has to do it…
3d nand word line stack uniformity prediction machine learning, 3d nand, word line stack, 3d nand word line stack uniformity prediction, 3d nand word, nand word line
3D NAND Word Line Stack Uniformity Prediction with Machine Learning Introduction & Motivation 3D NAND Word Line Stack Uniformity Prediction with Machine Learning addresses…
3d object detection lidar, 3d object detection, object detection lidar, 3d object, object detection, detection lidar
3D Object Detection LIDAR Introduction & Motivation 3D Object Detection LIDAR addresses a central problem in vision process control and 3d-detection-bounding-box prediction: how…
3d object detection point cloud, 3d object detection, object detection point, detection point cloud, 3d object, object detection, detection point, point cloud
3D Object Detection Point Cloud Introduction & Motivation 3D Object Detection Point Cloud addresses a central problem in robotics process control…
3d reconstruction sfm, 3d reconstruction, reconstruction sfm
3D Reconstruction SFM Introduction & Motivation 3D Reconstruction SFM addresses a central problem in vision process control and structure-motion-camera-pose prediction: how…
computer vision
3D scene reconstruction is the process of creating three-dimensional models of real-world environments from images or sensor data — recovering the geometry, structure…
monolithic 3d, cfet vertical stack, sequential mosfet, 3d si stacking, monolithic 3dic
3D Sequential Monolithic Integration is the advanced transistor stacking technology where multiple active device tiers are fabricated one on top of another on a single wafer using…
3d generation, generative ai, text to 3d, mesh generation, 3d vision, 3d modeling
3D shape generation is the computational process of synthesizing three-dimensional geometry representations from data, prompts, or procedural rules - it spans meshes, voxels…
3d ic tsv chiplet stack, logic memory stacking, 3d power delivery 3d, 3d thermal management stacked, hbm
High-bandwidth memory (HBM) is DRAM stacked vertically and connected to its host through an interface thousands of bits wide, running beside the processor on an interposer rather…
3d stacked die thermal cross-talk prediction, 3d stacked die, stacked die thermal, die thermal cross-talk, thermal cross-talk prediction, 3d stacked, stacked die
3D Stacked Die Thermal Cross-Talk Prediction with Machine Learning Introduction & Motivation 3D Stacked Die Thermal Cross-Talk Prediction with Machine Learning addresses a central…
3d stacked die thermal gradient prediction, 3d stacked die, stacked die thermal, die thermal gradient, thermal gradient prediction, 3d stacked, stacked die, die thermal
3D Stacked Die Thermal Gradient Prediction with Machine Learning Introduction & Motivation 3D Stacked Die Thermal Gradient Prediction with Machine Learning addresses a central…
3d chip stacking and thermal coupling between layers, 3d chip stacking, chip stacking thermal, stacking thermal coupling, thermal coupling between, coupling between layers, 3d chip
3D Chip Stacking and Thermal Coupling Between Layers Introduction & Motivation 3D Chip Stacking and Thermal Coupling Between Layers addresses a central problem in thermal process…
3d, advanced packaging
3D Stacking via Bonding is the process of vertically integrating multiple semiconductor dies or wafers by bonding them face-to-face or face-to-back — creating three-dimensional…
3d stacking and thermal, 3d stacking thermal, 3d stacking, stacking thermal
3D Stacking and Thermal Introduction & Motivation 3D Stacking and Thermal addresses a central problem in thermal process control and thermal-resistance prediction: how to Predict…
3d stacking and thermal coupling management, 3d stacking thermal, stacking thermal coupling, thermal coupling management, 3d stacking, stacking thermal, thermal coupling, coupling management
3D Stacking and Thermal Coupling Management Introduction & Motivation 3D Stacking and Thermal Coupling Management addresses a central problem in thermal process control…
predicting hotspot locations and magnitudes in 3d stacked devices, predicting hotspot locations, hotspot locations magnitudes, locations magnitudes 3d, magnitudes 3d stacked, hotspot locations
Predicting hotspot locations and magnitudes in 3D stacked devices Introduction & Motivation Predicting hotspot locations and magnitudes in 3D stacked devices addresses a central…
3d stacking and thermal coupling, 3d stacking thermal, stacking thermal coupling, 3d stacking, stacking thermal, thermal coupling
3D Stacking and Thermal Coupling Introduction & Motivation 3D Stacking and Thermal Coupling addresses a central problem in thermal process control and inter-die-thermal…
3d thermal transient analysis prediction, 3d thermal transient, thermal transient analysis, transient analysis prediction, 3d thermal, thermal transient, transient analysis
3D Thermal Transient Analysis Prediction with Machine Learning Introduction & Motivation 3D Thermal Transient Analysis Prediction with Machine Learning addresses a central problem…
hierarchical sampling methods, multi-resolution sampling
Hierarchical sampling is the two-stage ray-sampling method that allocates more samples to high-importance regions identified by an initial coarse pass - it concentrates compute…
3d xpoint, what is 3d xpoint
3D XPoint is a nonvolatile memory technology announced by Intel and Micron in July 2015. The name refers to a cross-point array architecture with cells accessed at intersecting…
what is 3dfx, 3dfx definition
3dfx was a graphics-technology company closely associated with the Voodoo family of PC 3D accelerators. Its role in the 1990s was the acceleration of rendering workloads that were…
3nm node parasitic extraction accuracy prediction, 3nm node parasitic, node parasitic extraction, parasitic extraction accuracy, extraction accuracy prediction, 3nm node
3nm Node Parasitic Extraction Accuracy Prediction with Machine Learning Introduction & Motivation 3nm Node Parasitic Extraction Accuracy Prediction with Machine Learning addresses…
3nm process, what is 3nm process
A label shared by different transistor choices. A 3nm process denotes a supplier’s advanced logic generation, rather than a common physical gate dimension. The generation is…
wafer size, wafer diameter, chips per wafer, wafer-size transition, 100mm wafer
The 4-inch wafer refers to a generation of silicon wafers roughly four inches in diameter that became a widespread manufacturing standard around the late 1970s and early 1980s…
4Kb DRAM, Mostek MK4096, address multiplexing, DRAM density generation, memory competition
The 4-kilobit DRAM is the second major density generation of dynamic random-access memory, a chip holding 4,096 bits, four times the capacity of the 1-kilobit generation that…
4Mb DRAM, elaborate cell capacitor, Korean memory makers, Samsung DRAM, memory competition
The 4-megabit DRAM is the density generation of dynamic memory storing roughly four million bits per chip, four times the 1-megabit generation, reaching the market around the end…
400 layer 3d nand, 3d nand flash, 3d nand, nand flash memory, 3d nand cua, cmos under array, har etch 3d nand, 400-layer nand flash, cryogenic etch 3d nand, string stacking 3d nand
400-Layer 3D NAND: High-Aspect-Ratio Etch Physics, Multi-Deck Architecture, and the Flash Scaling Moat 400-Layer 3D NAND Flash represents the pinnacle of three-dimensional…
450 mm wafer proposal, what is 450 mm wafer proposal
The 450 mm wafer proposal sought a larger silicon platform than the established 300 mm diameter. A 450 mm wafer has 1.5 times the diameter and 2.25 times the geometric area of…
45 nm process, what is 45 nm process
The 45 nm generation is closely associated with Intel’s adoption of high-k and metal-gate transistors. Intel publicly described the materials change in January 2007. The high-k…
busbar, power shelf, datacenter power delivery, rack power delivery, psu, pdu, point of load, voltage regulator module
Datacenter power delivery is the unglamorous logistics problem underneath every AI cluster: taking tens of megawatts from the utility grid and delivering it, at high efficiency…
temporal 3d, dynamic scene understanding
4D Scene Understanding extends 3D scene analysis to include temporal dynamics, enabling AI systems to perceive and predict how 3D environments change over time. What Is 4D Scene…