2,310 technical terms and definitions
hbm memory, gpu memory, vram, inference bottleneck, a100, h100
High-bandwidth memory (HBM) is DRAM stacked vertically and connected to its host through an interface thousands of bits wide, running beside the processor on an interposer rather…
hbm memory, memory stacking, 3d memory, dram stacking
High-bandwidth memory (HBM) is DRAM stacked vertically and connected to its host through an interface thousands of bits wide, running beside the processor on an interposer rather…
hbm strategy, business strategy, memory market
High-bandwidth memory (HBM) is DRAM stacked vertically and connected to its host through an interface thousands of bits wide, running beside the processor on an interposer rather…
hbm stacking, hbm process, wide io memory, hbm3
High-bandwidth memory (HBM) is DRAM stacked vertically and connected to its host through an interface thousands of bits wide, running beside the processor on an interposer rather…
bandwidth bound kernel, memory throughput, dram bandwidth, bandwidth efficiency, roofline memory
High-bandwidth memory (HBM) is DRAM stacked vertically and connected to its host through an interface thousands of bits wide, running beside the processor on an interposer rather…
memory bandwidth saturation and contention scaling, memory bandwidth saturation, bandwidth saturation contention, saturation contention scaling, memory bandwidth, bandwidth saturation
Memory Bandwidth Saturation and Contention Scaling Introduction & Motivation Memory Bandwidth Saturation and Contention Scaling addresses a central problem in memory process…
shared memory bandwidth efficiency in heterogeneous systems, shared memory bandwidth, memory bandwidth efficiency, bandwidth efficiency heterogeneous, shared memory
Shared Memory Bandwidth Efficiency in Heterogeneous Systems Introduction & Motivation Shared Memory Bandwidth Efficiency in Heterogeneous Systems addresses a central problem…
memory bandwidth sharing and priority allocation, memory bandwidth sharing, bandwidth sharing priority, sharing priority allocation, memory bandwidth, bandwidth sharing
Memory Bandwidth Sharing and Priority Allocation Introduction & Motivation Memory Bandwidth Sharing and Priority Allocation addresses a central problem in memory process control…
memory bandwidth utilization efficiency prediction, memory bandwidth utilization, bandwidth utilization efficiency, utilization efficiency prediction
Memory Bandwidth Utilization Efficiency Prediction with Machine Learning Introduction & Motivation Memory Bandwidth Utilization Efficiency Prediction with Machine Learning…
memory bandwidth utilization prediction, memory bandwidth utilization, bandwidth utilization prediction, memory bandwidth, bandwidth utilization, utilization prediction
Memory Bandwidth Utilization Prediction with Machine Learning Introduction & Motivation Memory Bandwidth Utilization Prediction with Machine Learning addresses a central problem…
self-supervised learning
Memory Bank is a data structure used in contrastive self-supervised learning to store a large collection of negative sample representations — enabling effective contrastive…
memory fence, memory ordering
Memory Barrier / Fence — a CPU instruction that enforces ordering of memory operations, preventing the hardware from reordering reads and writes in ways that break concurrent…
memory barrier synchronization, memory barrier, barrier synchronization
Memory Barrier Synchronization Introduction & Motivation Memory Barrier Synchronization addresses a central problem in systems process control and barrier-overhead-latency-cost…
advanced test & probe
Memory BIST is specialized built-in self-test for embedded memories using programmable march and stress algorithms - MBIST controllers run memory-specific test sequences to detect…
design & verification
Design-for-test architectures, automatic test pattern generation, and structural fault modeling constitute the digital verification and manufacturing test disciplines engineered…
mbist, built in self test memory, sram bist, memory test pattern
Design-for-test architectures, automatic test pattern generation, and structural fault modeling constitute the digital verification and manufacturing test disciplines engineered…
built in self test, mbist, memory test, sram bist, repair analysis
Design-for-test architectures, automatic test pattern generation, and structural fault modeling constitute the digital verification and manufacturing test disciplines engineered…
mbist controller algorithm, march test pattern memory, bist repair analysis, sram bist test coverage
Design-for-test architectures, automatic test pattern generation, and structural fault modeling constitute the digital verification and manufacturing test disciplines engineered…
memory bist fault coverage prediction, memory bist fault, bist fault coverage, fault coverage prediction, memory bist, bist fault, fault coverage, coverage prediction
Memory BIST Fault Coverage Prediction with Machine Learning Introduction & Motivation Memory BIST Fault Coverage Prediction with Machine Learning addresses a central problem…
mbist architecture controller, mbist march algorithm, mbist repair analysis, mbist self test memory
Design-for-test architectures, automatic test pattern generation, and structural fault modeling constitute the digital verification and manufacturing test disciplines engineered…
memory bist repair analysis prediction, memory bist repair, bist repair analysis, repair analysis prediction, memory bist, bist repair, repair analysis, analysis prediction
Memory BIST Repair Analysis Prediction with Machine Learning Introduction & Motivation Memory BIST Repair Analysis Prediction with Machine Learning addresses a central problem…
memory-bound, bandwidth bound, arithmetic intensity, roofline bandwidth ceiling
Memory bound describes a workload whose elapsed time is limited primarily by data supply rather than arithmetic capability. It explains why enormous advertised FLOPS can remain…
model optimization
Memory-Bound Operations is operators whose performance is limited mainly by memory bandwidth rather than arithmetic throughput - They often dominate latency in real inference…
continual learning
A memory buffer in continual learning is a fixed-size storage that holds representative examples from previously learned tasks, enabling rehearsal and preventing catastrophic…
memory bus architecture, memory bus, bus architecture
Memory Bus Architecture Introduction & Motivation Memory Bus Architecture addresses a central problem in memory-architecture process control and bus-bandwidth-gb-per-sec…
memory bus signal integrity prediction, memory bus signal, bus signal integrity, signal integrity prediction, memory bus, bus signal, signal integrity, integrity prediction
Memory Bus Signal Integrity Prediction with Machine Learning Introduction & Motivation Memory Bus Signal Integrity Prediction with Machine Learning addresses a central problem…
memory cell retention time prediction, memory cell retention, cell retention time, retention time prediction, memory cell, cell retention, retention time, time prediction
Memory Cell Retention Time Prediction with Machine Learning Introduction & Motivation Memory Cell Retention Time Prediction with Machine Learning addresses a central problem…
memory cell variability modeling, memory cell variability, cell variability modeling, memory cell, cell variability, variability modeling
Memory Cell Variability Modeling with Machine Learning Introduction & Motivation Memory Cell Variability Modeling with Machine Learning addresses a central problem in memory cell…
memory design characterizing and predicting cell-to-cell variability in memory arrays, memory design characterizing, design characterizing predicting, characterizing predicting cell-to-cell
Memory Design: Characterizing and predicting cell-to-cell variability in memory arrays Introduction & Motivation Memory Design: Characterizing and predicting cell-to-cell…
characterizing and predicting cell-to-cell variability in memory arrays, characterizing predicting cell-to-cell, predicting cell-to-cell variability, cell-to-cell variability memory
Characterizing and predicting cell-to-cell variability in memory arrays Introduction & Motivation Characterizing and predicting cell-to-cell variability in memory arrays addresses…
processing in memory, near data processing, computational memory units, data movement reduction
Memory-Centric Computing Architectures — Design paradigms that place memory at the center of computation, minimizing data movement by bringing processing capabilities closer…
access pattern
Memory coalescing is a critical GPU optimization where adjacent threads access adjacent memory locations, enabling the hardware to combine multiple memory requests into single…
optimization
Memory coalescing is the access pattern optimization where neighboring threads read or write contiguous addresses in combined transactions - it is one of the highest-impact…
coalesced access, gpu memory access pattern
Memory Coalescing — organizing GPU global memory access patterns so that threads in a warp access consecutive memory addresses, allowing the hardware to combine individual…
coalesced memory access, structure of arrays soa, memory access patterns gpu, stride memory access
Memory Coalescing Optimization is the critical technique of arranging memory access patterns so that threads within a warp access consecutive memory addresses — enabling the GPU…
memory coherence protocol scalability and directory overhead, memory coherence protocol, coherence protocol scalability, protocol scalability directory, memory coherence
Memory Coherence Protocol Scalability and Directory Overhead Introduction & Motivation Memory Coherence Protocol Scalability and Directory Overhead addresses a central problem…
sram macro, memory macro generation, cacti memory, memory ip generator, sram compiler tool
Memory Compiler is the automated EDA tool that generates custom SRAM, ROM, or register file macros for a specific foundry process, automatically producing the full set of design…
memory compiler cell yield optimization, memory compiler cell, compiler cell yield, cell yield optimization, memory compiler, compiler cell, cell yield, yield optimization
Memory Compiler Cell Yield Optimization with Machine Learning Introduction & Motivation Memory Compiler Cell Yield Optimization with Machine Learning addresses a central problem…
SRAM compiler, register file compiler, memory generator
Memory Compiler Design is the creation of parameterized generators that automatically produce custom SRAM, register file, ROM, and other memory instances with user-specified…
sram bitcell design, memory macro generator, register file design, custom memory design
Memory Compiler and SRAM Design is the EDA tool and custom circuit design discipline that generates optimized, foundry-qualified memory macros (SRAM, register files, ROM, CAM)…
sram design, memory macro generator, register file design, sram cell layout
Memory Compiler and SRAM Design is the automated IP generation system that creates custom SRAM, register file, and ROM macros tailored to the exact word depth, bit width, port…
sram bitcell architecture, memory array organization, sense amplifier design, embedded memory generation
Memory Compiler and SRAM Design — Memory compilers generate customized SRAM instances with specified configurations of word depth, bit width, and port count, producing optimized…
memory ordering, sequential consistency, relaxed consistency, total store order
Memory Consistency Models define the formal rules governing the order in which memory operations (loads and stores) performed by one processor become visible to other processors…
consistency vs coherence, sequential consistency, relaxed memory model
Memory Consistency Models define the formal rules governing the order in which memory operations (loads and stores) from different threads or processors appear to execute…
sequential consistency, relaxed consistency, acquire release semantics, memory ordering parallel
Memory Consistency Models define the contractual rules governing the order in which memory operations (loads and stores) from different threads become visible to each other…
sequential consistency, relaxed memory order, memory barrier fence, memory ordering parallel
Memory Consistency Models are the formal specifications that define the order in which memory operations (loads and stores) from different threads or processors become visible…
sequential consistency model, total store order tso, release consistency, memory ordering hardware
Memory Consistency Models are the formal specifications that define the legal orderings of memory operations (loads and stores) as observed by different processors in…
sequential consistency total store order, acquire release semantics, memory ordering concurrent, memory barrier fence
Memory Consistency Models define the rules governing when stores performed by one processor become visible to loads performed by other processors — establishing the contract…
sequential consistency relaxed, total store order model, release acquire semantics, memory ordering guarantees
Memory Consistency Models — Memory consistency models define the rules governing the order in which memory operations from different processors become visible to each other…
sequential consistency relaxed, total store order memory, release consistency acquire, memory ordering guarantees
Memory Consistency Models are formal specifications that define the order in which memory operations (loads and stores) performed by one processor become visible to other…