2,847 technical terms and definitions
CPU, fetch-decode-execute cycle, instruction cycle, program counter, instruction register, von Neumann architecture, Intel 4004
The central processing unit, or CPU, is the part of a computer that runs programs: it repeatedly fetches an instruction from memory, works out what that instruction asks for…
measures of central tendency, average, typical value, location measure, measure of location, centre of a distribution
Central tendency is the statistical idea of a single value that represents the centre or typical position of a dataset, around which the observations cluster, and the measures…
centralized architecture throughput prediction, centralized architecture throughput, architecture throughput prediction, centralized architecture, architecture throughput
Centralized Architecture Throughput Prediction with Machine Learning Introduction & Motivation Centralized Architecture Throughput Prediction with Machine Learning addresses…
ceramic capacitor voltage coefficient prediction, ceramic capacitor voltage, capacitor voltage coefficient, voltage coefficient prediction, ceramic capacitor
Ceramic Capacitor Voltage Coefficient Prediction with Machine Learning Introduction & Motivation Ceramic Capacitor Voltage Coefficient Prediction with Machine Learning addresses…
cerdip, packaging
Ceramic DIP is the dual in-line package variant using ceramic body materials for enhanced thermal stability and hermetic performance - it is used in high-reliability…
ceramic heater element remaining life prediction machine learning, ceramic heater, element remaining life, ceramic heater element remaining life prediction
Ceramic Heater Element Remaining Life Prediction with Machine Learning Introduction & Motivation Ceramic Heater Element Remaining Life Prediction with Machine Learning addresses…
ceramic package braze void prediction machine learning, ceramic package, braze void prediction, ceramic package braze void prediction, ceramic package braze, package braze void
Ceramic Package Braze Void Prediction with Machine Learning Introduction & Motivation Ceramic Package Braze Void Prediction with Machine Learning addresses a central problem…
ceramic package metallization adhesion prediction, ceramic package metallization, package metallization adhesion, metallization adhesion prediction, ceramic package
Ceramic Package Metallization Adhesion Prediction with Machine Learning Introduction & Motivation Ceramic Package Metallization Adhesion Prediction with Machine Learning addresses…
packaging
Ceramic PGA is the pin grid array package using ceramic substrate materials for high thermal stability and reliability - it is suited to high-performance and mission-critical…
cerebras, open
Cerebras-GPT is a family of decoder-only transformer models (111M to 13B parameters) open-sourced by Cerebras Systems with published scaling laws and trained on 256B tokens…
certificate authority pki, certificate authority, authority pki
Certificate Authority PKI Introduction & Motivation Certificate Authority PKI addresses a central problem in cryptography process control and certificate-chain-validation…
certificate of conformance anomaly prediction, certificate conformance anomaly, conformance anomaly prediction, certificate conformance, conformance anomaly, anomaly prediction
Certificate of Conformance Anomaly Prediction with Machine Learning Introduction & Motivation Certificate of Conformance Anomaly Prediction with Machine Learning addresses…
quality & reliability
Certification is formal authorization granting personnel permission to perform defined operations independently - It is a core method in modern semiconductor operational…
provable, bound
Certified Robustness is the formal guarantee that a neural network's prediction cannot be changed by any perturbation within a specified distance of an input — providing…
interpretability
Certified Defense is defense methods that provide formal guarantees of model robustness within bounded perturbations - It moves robustness claims from empirical evidence…
evaluation
Certified Fairness is formal guarantees that model outputs satisfy fairness bounds under specified assumptions - It is a core method in modern AI fairness and evaluation…
crm, quality
CRM (Certified Reference Material) is a reference material with one or more property values certified by a metrologically valid procedure, accompanied by a certificate with stated…
ai safety
Certified robustness provides mathematical proofs that model predictions are invariant within specified input perturbation bounds, offering formal guarantees against adversarial…
certified robustness, robustness provable, ai cifar ibp mnist, certified robustness & provable defenses, certified robustness provable, robustness provable defenses, provable defenses
Certified Robustness & Provable Defenses Introduction & Motivation Certified robustness: prove model robustness formally. Provide robustness guarantees. Applications…
ai safety
Certified Robustness Verification is the mathematical guarantee that a neural network's prediction is provably correct within a specified perturbation radius — providing formal…
Certified Robustness via Randomized Smoothing Introduction & Motivation Certified Robustness via Randomized Smoothing addresses a central problem in robustness of advrobust models…
Certified Robustness via Randomized Smoothing (Extended Study) Introduction & Motivation Certified Robustness via Randomized Smoothing (Extended Study) addresses a central problem…
Certified Robustness via Randomized Smoothing (Extended Study) Introduction & Motivation Certified Robustness via Randomized Smoothing (Extended Study) addresses a central problem…
Certified Robustness via Randomized Smoothing (Extended Study) Introduction & Motivation Certified Robustness via Randomized Smoothing (Extended Study) addresses a central problem…
cfd, thermal management
CFD thermal is computational fluid dynamics modeling used to analyze airflow and heat transfer in electronic assemblies - CFD resolves fluid motion and convective transport…
complementary fet, stacked transistor
CFET (Complementary FET) is an advanced transistor architecture that vertically stacks nFET and pFET devices to dramatically reduce logic cell area beyond FinFET and nanosheet…
complementary fet, stacked transistor, stacked cmos, cfet process
CFET — the complementary FET — is the transistor architecture the industry expects to follow the nanosheet gate-all-around device, the next rung on a scaling ladder that already…
cfet, complementary fet, technology, complementary field effect transistor, cfet vs gaa, 3d stacked transistor, transistor after nanosheet
CFET — the complementary FET — is the transistor architecture the industry expects to follow the nanosheet gate-all-around device, the next rung on a scaling ladder that already…
stacked transistor nmos pmos, cfet integration process, stacked nanosheet cfet, 3d transistor scaling
Gate-All-Around (GAA) nanosheet field-effect transistors, Multi-Bridge Channel FETs (MBCFET), and vertically stacked ribbon architectures constitute the advanced three-dimensional…
stacked nmos pmos, cfet transistor architecture, vertically stacked cmos, cfet beyond nanosheet
Gate-All-Around (GAA) nanosheet field-effect transistors, Multi-Bridge Channel FETs (MBCFET), and vertically stacked ribbon architectures constitute the advanced three-dimensional…
cfet logic step 1 confront the standard cell area wall, confront the standard cell area wall nanosheet gaa leaves open
CFET (Complementary FET): Step 1 — Confront the Standard-Cell Area Wall Nanosheet GAA Leaves Open 1. Where `gaa_nanosheet_2020s` Left the Area Question That series' own Step 15…
cfet logic step 2 establish vertical device stacking as the, establish vertical device stacking as the remaining scaling axis
CFET (Complementary FET): Step 2 — Establish Vertical Device Stacking as the Remaining Scaling Axis 1. The Core Structural Move CFET's defining change is simple to state and hard…
cfet logic step 3 distinguish forksheet as a transitional step, distinguish forksheet as a transitional step before full cfet
CFET (Complementary FET): Step 3 — Distinguish Forksheet as a Transitional Step Before Full CFET 1. Why This Distinction Matters Early `gaa_nanosheet_2020s` Step 11 named…
cfet logic step 4 weigh monolithic cfet integration one continuous, weigh monolithic cfet integration one continuous fabrication sequence
CFET (Complementary FET): Step 4 — Weigh Monolithic CFET Integration: One Continuous Fabrication Sequence 1. The Monolithic Approach, Defined Monolithic CFET builds the bottom…
cfet logic step 5 weigh sequential cfet integration bonding a, weigh sequential cfet integration bonding a second wafer for the top device
CFET (Complementary FET): Step 5 — Weigh Sequential CFET Integration: Bonding a Second Wafer for the Top Device 1. The Sequential Approach, Defined Sequential CFET builds…
cfet logic step 6 compare monolithic thermal budget against sequential, compare monolithic thermal budget against sequential bonding and alignment yield
CFET (Complementary FET): Step 6 — Compare Monolithic Thermal Budget Against Sequential Bonding and Alignment Yield 1. Two Problems, Neither One Solved by Avoiding the Other Steps…
cfet logic step 7 isolate the stacked nmos and pmos, isolate the stacked nmos and pmos channels with a middle dielectric
CFET (Complementary FET): Step 7 — Isolate the Stacked NMOS and PMOS Channels With a Middle Dielectric 1. Why the Stack Needs an Internal Isolation Layer With the bottom NMOS…
cfet logic step 8 confront the shared gate versus independent, confront the shared gate versus independent gate question
CFET (Complementary FET): Step 8 — Confront the Shared-Gate Versus Independent-Gate Question 1. A Question the Stack Forces With the NMOS and PMOS channels isolated from each…
cfet logic step 9 weigh why independent gate contacts matter, weigh why independent gate contacts matter for circuit design flexibility
CFET (Complementary FET): Step 9 — Weigh Why Independent Gate Contacts Matter for Circuit Design Flexibility 1. Beyond the Inverter Case Step 8 framed…
cfet logic step 10 route independent source drain contacts to, route independent source drain contacts to both stacked devices
CFET (Complementary FET): Step 10 — Route Independent Source/Drain Contacts to Both Stacked Devices 1. A Genuinely Hard Interconnect Problem Every transistor needs its source…
cfet logic step 11 demonstrate cfet with the inverter as, demonstrate cfet with the inverter as the simplest test circuit
CFET (Complementary FET): Step 11 — Demonstrate CFET With the Inverter as the Simplest Test Circuit 1. Why the Inverter Is CFET's Natural First Demonstration An inverter needs…
cfet logic step 12 walk through why vertical stacking halves, walk through why vertical stacking halves standard cell height
CFET (Complementary FET): Step 12 — Walk Through Why Vertical Stacking Halves Standard-Cell Height 1. Cell Height, Defined A standard cell's height is the vertical dimension…
cfet logic step 13 redesign the standard cell library and, redesign the standard cell library and design rules around cfet
CFET (Complementary FET): Step 13 — Redesign the Standard-Cell Library and Design Rules Around CFET 1. Why a New Library, Not Just New Cells `gaa_nanosheet_2020s` Step 15…
cfet logic step 14 confront process complexity and cost as, confront process complexity and cost as a harder sell than prior transitions
CFET (Complementary FET): Step 14 — Confront Process Complexity and Cost as a Harder Sell Than Prior Transitions 1. Comparing This Transition to Its Predecessors Every…
cfet logic step 15 elevate backside power delivery s role, elevate backside power delivery s role once cfet removes lateral routing room
CFET (Complementary FET): Step 15 — Elevate Backside Power Delivery's Role Once CFET Removes Lateral Routing Room 1. Backside Power Delivery, Recapped `gaa_nanosheet_2020s` Step…
cfet logic step 16 extend cfet from the inverter to, extend cfet from the inverter to multi device complex logic gates
CFET (Complementary FET): Step 16 — Extend CFET From the Inverter to Multi-Device Complex Logic Gates 1. Where the One-Stack-Per-Cell Picture Breaks Step 12 showed that…
cfet logic step 17 weigh industry r d status and, weigh industry r d status and timelines honestly
CFET (Complementary FET): Step 17 — Weigh Industry R&D Status and Timelines Honestly 1. What "Demonstrated" Means Here Research groups and major foundries have reported working…
cfet logic step 18 position cfet as a leading candidate, position cfet as a leading candidate for scaling beyond nanosheet
CFET (Complementary FET): Step 18 — Position CFET as a Leading Candidate for Scaling Beyond Nanosheet 1. Why "Leading Candidate" Is the Right Level of Claim Across the research…
cfet logic step 19 synthesize cfet s cost complexity and, synthesize cfet s cost complexity and benefit tradeoff honestly
CFET (Complementary FET): Step 19 — Synthesize CFET's Cost, Complexity, and Benefit Tradeoff Honestly 1. Pulling the Series' Threads Together This series has, across 18 prior…
cfet logic step 20 close the series cfet as an, close the series cfet as an actively researched direction not a settled outcome
CFET (Complementary FET): Step 20 — Close the Series: CFET as an Actively Researched Direction, Not a Settled Outcome 1. What This Series Has Covered Twenty steps have walked…