1,012 technical terms and definitions
nitride oxide nitride spacer, N O N multilayer spacer, storage node contact self alignment, bitline parasitic capacitance
The bitline spacer etch forms a multilayer nitride-oxide-nitride sidewall around the finished bitline conductor stack, and it is a genuinely different problem from…
BWL etch, WL trench, gate trench DRAM, saddle fin recess, GIDL control, BCAT transistor
The buried wordline trench etch — called BWL Etch, WL Trench, or Gate Trench depending on the maker — carves the channel for a DRAM access transistor's gate down into the silicon…
experimental mos bipolar logic step 3 surface passivated mos structure first working device, atalla kahng mos transistor 1960
Build the First Working MOS Transistor: Atalla and Kahngs Surface-Passivated Structure 1. Why This Specific Structure, Built at Bell Labs in 1959-1960, Finally Worked Mohamed…
grown junction 1951 begin crystal pulling, stefan condition crystal growth interface, withdraw the seed czochralski, grown junction transistor interface velocity
Begin Crystal Pulling: Reversing the Interface from Dissolving to Growing Step nine deliberately dissolved seed material into the melt; step ten has to reverse that exact…
hbm base die, base die, hbm4 base logic die, memory controller die, hbm logic die, custom base die, hbm phy
The base logic die is the bottom die of an HBM stack: the layer that aggregates every TSV column from the DRAM dies above it, runs the physical interface to the host, and handles…
local oxidation of silicon, locos isolation, nitride mask oxidation encroachment
LOCOS Bird's Beak Before shallow trench isolation existed, fabs separated transistors with LOCOS — local oxidation of silicon — and LOCOS had a built-in flaw baked into its own…
mask rom addressing step 10 build a business out, build a business
Build a Business Out of Fixed, Mass-Produced Game Data: the Cartridge ROM 1. Sell a Mask ROM as the Product Itself A game cartridge put a mask-programmed ROM holding a complete…
boson quantum distribution, bose einstein condensation bec, phonon occupancy lattice thermal conductivity, debye heat capacity, photonic stimulated emission, semiconductor quantum statistics
Bose–Einstein Statistics: Bosonic Occupation Physics, Lattice Phonons, and Photonic Quantum Phenomena in Semiconductors Executive Overview Bose–Einstein (BE) statistics governs…
sram six transistor step 2 cross coupled inverter pair, cross coupled inverter bistable latch
Build the Cross-Coupled Inverter Pair as a Bistable Storage Element 2. Build the Cross-Coupled Inverter Pair as a Bistable Storage Element The core of every SRAM cell is not…
tan copper diffusion barrier, amorphous barrier grain boundary, copper seed layer barrier
Tantalum Nitride Diffusion Barrier Copper interconnect only became possible once the industry solved a problem copper itself creates: copper diffuses readily through silicon…
A ball grid array, or BGA, is a chip packaging method that uses a grid of small solder balls on the underside of the package to connect it to a circuit board, replacing…
Backside power delivery is a chip design approach that moves the power distribution network from the front side of the wafer, where signal wiring lives, to the back side, freeing…