bake schedule
packaging
Bake schedule is the defined temperature-time profile used to remove absorbed moisture from components before assembly - it converts moisture-risk conditions into controlled…
3,802 technical terms and definitions
packaging
Bake schedule is the defined temperature-time profile used to remove absorbed moisture from components before assembly - it converts moisture-risk conditions into controlled…
packaging
Ball bonding is the wire bonding technique where a spherical free-air ball is formed at wire tip to create the first bond on the die pad - it is commonly used with gold or copper…
bga, packaging, solder ball, perimeter lead package, X-ray inspection, reflow uniformity, thermal ball, ground ball, high I/O package
A ball grid array (BGA) is a package format that connects a chip to its circuit board through a grid of solder balls on its underside, rather than through leads sticking out…
semiconductor band gap, direct indirect bandgap, wide bandgap materials, bandgap engineering
The band gap Eg is the energy separation between the top of the valence band and the bottom of the conduction band, and it is the single parameter that decides whether a crystal…
bottom antireflective coating, bottom anti-reflective coating, barc (bottom arc), bottom arc, arc lithography, standing wave suppression, refractive index matching 193nm, organic inorganic barc, euv underlayer
Bottom antireflective coating is a thin film applied between photoresist and substrate to suppress optical reflections during lithographic exposure, reducing standing-wave…
bardeen brattain 1947 step 2 cut germanium body, cut small block or disc germanium, saw damage machining allowance germanium body, create the semiconductor body point contact
Cut a Small Block or Disc: The First Operation That Can Destroy What Step 1 Selected For Step 1 accepted a germanium sample on the strength of a property that lives in the bulk…
bardeen brattain 1947 step 7 reetch upper face, re-etch the upper face germanium contamination, stray metal contamination threshold surface states, conditional step line of sight deposition germanium
Re-Etch the Upper Face: The First Step in This Sequence That Might Not Run at All Every step so far has run unconditionally — the sample selected in Step 1 either passed its…
tantalum nitride barrier, pvd ald barrier, copper diffusion prevention, conformal liner coverage
Copper dual damascene interconnect architectures, electrochemical superfilling, and barrier-seed metallization constitute the back-end-of-line (BEOL) wiring systems that route…
copper dual damascene, interconnect rc delay optimization, barrier seed deposition, low-k dielectric integration
Copper dual damascene interconnect architectures, electrochemical superfilling, and barrier-seed metallization constitute the back-end-of-line (BEOL) wiring systems that route…
wafer edge profile, semi m1
Bevel Edge refers to the angled profile machined into wafer edges during manufacturing, typically at 15-22° angles to reduce chipping and improve handling. What Is a Bevel Edge?…
alternative channel materials, ge iii-v channels, 2d material transistors, high mobility channels, germanium p-channel, iii-v semiconductor, mos2 transistor, graphene channel, monolayer transistors, carrier mobility
Beyond-silicon channel materials—germanium, III-V semiconductors, and two-dimensional crystals—address the escalating challenges of Si scaling by offering superior carrier…
packaging, stand-off height, ball-attach process, incoming quality, reflow collapse, thermal cycle fatigue, solder volume, ball diameter distribution, reliability correlation
BGA ball diameter is the nominal size of each individual solder sphere on a BGA package before reflow, and it's the single number that most directly sets how much solder material…
bga, packaging, bga ball diameter, solder joint volume, thermal fatigue, fine pitch assembly, escape routing, stand-off height, PCB fabrication tolerance
Ball pitch and ball diameter are the two geometric numbers that define a BGA package's solder ball array — pitch is the center-to-center spacing between adjacent balls, diameter…
metrology
Bias in metrology is the systematic difference between the average measured value and the true (reference) value — a constant offset that affects accuracy (not precision), caused…
icp ccp, plasma etch icp ccp, icp plasma etching, ccp plasma etching, inductively coupled plasma, capacitively coupled plasma, wafer bias, bias power, rf bias etch, bias voltage plasma, etch bias control, ion energy etch, ccp bias
Plasma etching and reactor physics govern the dry, anisotropic material removal processes essential for patterning nanoscale semiconductor features. Driven by radio-frequency…
bipolar ecl 1960s step 18 manage thermal design and packaging for ecl, manage thermal design and packaging for ecl
Bipolar ECL Logic (1960s): Step 18 — Managing Thermal Design and Packaging for ECL The physical engineering problem created by Step 11's power-dissipation finding. A board densely…
Best Known Method, Best Known Methods, semiconductor BKM, foundry BKM, process BKM, equipment BKM, maintenance BKM, metrology BKM, fab best known method, process of record, POR, tool matching, process control
BKM: Best Known Method in Semiconductor Foundry Operations A Best Known Method (BKM) is the currently preferred, documented, and validated way to execute a defined semiconductor…
blade dicing chipping prediction, blade dicing chipping, dicing chipping prediction, blade dicing, dicing chipping, chipping prediction
Blade Dicing Chipping Prediction with Machine Learning Introduction & Motivation Blade Dicing Chipping Prediction with Machine Learning addresses a central problem in mechanical…
lithography
Block Copolymer Lithography is a Directed Self-Assembly (DSA) technique that exploits thermodynamic phase separation of immiscible polymer blocks to spontaneously form periodic…
boat loading wafer spacing uniformity prediction machine learning, boat loading, wafer spacing uniformity, boat loading wafer spacing uniformity prediction
Boat Loading Wafer Spacing Uniformity Prediction with Machine Learning Introduction & Motivation Boat Loading Wafer Spacing Uniformity Prediction with Machine Learning addresses…
plasma sheath potential drop, iedf iadf distribution functions, reactive ion etching sheath kinetics, child-langmuir law plasma, aspect ratio dependent etching arde
Nonlinear Electrostatic Plasma Sheath Dynamics, Bohm Velocity Criterion, and Ion Distribution Modeling for Sub-5nm Reactive Ion Etching Executive Summary The plasma sheath—a thin…
advanced packaging
Bond Energy is the thermodynamic measure of adhesion strength at a bonded wafer interface, expressed as the energy per unit area (J/m²) required to separate the bonded surfaces…
advanced packaging
Bond Interface Characterization is the suite of analytical techniques used to evaluate the quality, integrity, and reliability of bonded wafer interfaces — measuring bond energy…
advanced packaging
Bond Strength is the quantitative measure of adhesion between bonded wafer surfaces — expressed as surface energy (J/m²) or mechanical stress (MPa) required to separate the bonded…
packaging
Bond strength is the mechanical robustness of wire-bond interfaces measured by their ability to withstand applied force without failure - it is a primary quality metric…
substrate
Silicon-on-Insulator (SOI) substrate engineering, Fully Depleted SOI (FD-SOI) planar architectures, and dynamic back-gate body biasing constitute the engineered substrate…
advanced packaging
Bonding Alignment is the precision mechanical process of registering the patterns on two wafers or dies to each other before bonding — achieving overlay accuracy from micrometers…
etch, drie, deep reactive ion etching, time multiplexed etch, bosch drie
The Bosch process, specifically designated as time-multiplexed pulsed Deep Reactive Ion Etching (DRIE), is a time-multiplexed anisotropic silicon plasma-etching method used…
advanced packaging, drie, deep reactive ion etching, tsv
Through-Silicon Vias are the vertical conductive interconnect pillars that traverse the bulk silicon substrate to establish high-density, low-latency electrical connections…
bossung curves, bossung plot, focus exposure matrix, fem bossung, isofocal dose, process window bossung, lithography
Bossung curves are experimental and optical simulation plots showing how printed critical dimension (CD) varies as a function of defocus across multiple exposure doses, serving as…
metrology
Breakdown voltage test measures the voltage at which a junction or dielectric fails — applying increasing voltage until current spikes dramatically, providing critical limits…
metrology
Metrology and inspection are the two measurement disciplines that keep a semiconductor fab in control — they are how a foundry knows, wafer by wafer, whether hundreds of process…
metrology
Brightfield inspection finds wafer anomalies by imaging reflected light and looking for departures from the expected pattern. The useful output is a set of candidate defect…
broadband plasma, bbp, bbp inspection, darkfield inspection, brightfield inspection, laser scattering defect inspection, nuisance defect filtering, wafer defect inspection, optical defect inspection
Broadband plasma defect inspection is the workhorse of unpatterned and patterned wafer inspection at advanced nodes. A laser-sustained plasma source can provide a broad UV-visible…
backside thinning grinding, backside passivation bsi, color filter array deposition, microlens array formation
Backside-illuminated image-sensor fabrication relocates the optical entrance to the substrate side of a completed pixel wafer. Frontside devices and interconnect are built first…
loose parts, manual assembly
Bulk packaging is the component supply method where parts are shipped loose in containers without individual pocketed orientation - it is generally suited to manual assembly…
box layer formation, smart cut wafer, soi wafer bonding, simox oxygen implant
Silicon-on-Insulator (SOI) substrate engineering, Fully Depleted SOI (FD-SOI) planar architectures, and dynamic back-gate body biasing constitute the engineered substrate…
burn in, semiconductor burn-in, reliability screening, early life failure
Burn-in is an accelerated product stress intended to precipitate early-life defects before shipment. Burn-in is used selectively in high-reliability semiconductor, memory…
amba axi, axi4, axi4 lite, axi stream, ace, chi, valid ready handshake, on chip bus
AXI protocol is the AMBA Advanced eXtensible Interface family used to connect masters, interconnects and slaves in many SoCs. Its independent channels, bursts, outstanding…
on chip bus, on chip interconnect, ahb, axi, chi, tilelink, crossbar, ring, noc, network on chip
Bus protocol defines how initiators, targets and interconnect transfer addresses, data, control, responses and ordering inside a chip. Interconnect architecture determines whether…
metrology
C-V curve (capacitance-voltage) measures capacitance across MOS structures vs. applied voltage — revealing oxide thickness, interface trap density, doping profiles, and threshold…
c4, packaging
C4 is the Controlled Collapse Chip Connection technology that uses solder bumps to create self-aligned flip-chip joints during reflow - it is a foundational method in modern…
electronic design automation, EDA company, chip design tools, design software, EDA market
Cadence is one of the major companies in electronic design automation, providing the software tools that chip designers use to design, simulate, verify, and lay out integrated…
calculus, partial differential equations, pde, calculus semiconductor, partial differential equations semiconductor, pde semiconductor, drift diffusion, heat equation, semiconductor calculus pdes
Calculus and partial differential equations are the mathematical language in which the physical laws governing semiconductor devices are written, and they form the bridge between…
low pressure LPCVD silicon dioxide, CVD process temperature pressure control, metal organic MOCVD compound semiconductor, polysilicon poly-Si deposition growth, conformal step coverage thin film, plasma enhanced PECVD dielectric
Chemical Vapor Deposition (CVD): Process Fundamentals, Reactor Design, and Integration in Advanced Semiconductor Manufacturing Executive Overview Chemical vapor deposition (CVD)…
metrology
Calibration Curve is a mathematical relationship between the instrument response and the known concentration or property value of calibration standards — typically a plot…
metrology
Caliper is a versatile measuring instrument capable of measuring external dimensions, internal dimensions, depths, and step heights — the most widely used dimensional measurement…
design services, design help, asic design, chip design services
Yes! We offer comprehensive chip design services from specification to tape-out including RTL design, verification, physical design, and IP integration with experienced teams…
Canon lithography, optics and imaging, exposure tool, lithography equipment supplier, wafer scanner
The Canon stepper refers to the lithography steppers and scanners made by the Japanese company Canon, another major supplier of wafer exposure equipment whose participation, like…
packaging
Cap wafer bonding is the wafer-to-wafer joining process that seals a device wafer with a cap wafer to protect sensitive structures and define cavity conditions - it is widely used…