3,801 technical terms and definitions
gate all around process, nanosheet stack epitaxy, nanosheet release etch, gaa transistor fabrication, gaa, nanosheet
Gate-All-Around (GAA) nanosheet field-effect transistors, Multi-Bridge Channel FETs (MBCFET), and vertically stacked ribbon architectures constitute the advanced three-dimensional…
nanosheet gaa process, nanosheet width tuning, nanosheet stack formation, nanosheet release etch, gaa, nanosheet
Nanosheet Transistor Fabrication: Unit Process Integration & Physics Nanosheet transistor fabrication is the primary semiconductor manufacturing methodology for leading-edge logic…
metrology
Nanotopography is the surface height variation on a wafer at spatial wavelengths between 0.2mm and 20mm — capturing medium-frequency surface features that are too large…
nanowire fet fabrication, nanowire channel formation, nanowire gaa device, vertical nanowire transistor
Nanowire Transistor Process: Channel Formation, 1D Transport & Vertical Scaling In advanced nanoelectronics, the Nanowire Field-Effect Transistor (NW-FET) represents the ultimate…
Japanese semiconductor maker, top chipmaker, DRAM memory, electronics and communications company, Japan semiconductor rise
NEC is a major Japanese electronics and communications company that was one of the leading semiconductor manufacturers during Japan's rise to prominence in the chip industry…
lithography, cross-linking resist, negative-tone resist
Negative photoresist is a light-sensitive polymeric coating that cross-links wherever ultraviolet radiation or electron-beam energy exposes it, rendering the exposed regions…
network on chip, noc, on chip network, mesh interconnect
A network on chip (NoC) is the packet-switched communication fabric that moves data among processors, accelerators, caches, memory controllers, and I/O blocks inside a system on…
noc router, mesh noc, noc latency bandwidth, on chip interconnect
Network-on-Chip (NoC) Architecture is the structured communication fabric that replaces ad-hoc wire-based interconnects with a packet-switched or circuit-switched network…
network-on-chip design
Network-On-Chip Design Introduction & Motivation Network-On-Chip Design addresses a central problem in chip-architecture process control and network-latency-hops prediction: how…
noc router, noc topology, system on chip interconnect, noc packet switching
Network-on-Chip (NoC) is the packet-switched communication architecture that replaces traditional shared buses or crossbar switches in complex Systems-on-Chip (SoCs), routing data…
noc mesh topology, noc router microarchitecture, noc arbitration, on-chip interconnect network
Network-on-Chip (NoC) Architecture is a scalable on-chip communication framework that replaces traditional bus-based interconnects with packet-switched networks, enabling…
on chip interconnect design, noc router switching fabric, mesh topology communication, quality of service noc
Network-on-Chip NoC Architecture — Network-on-chip (NoC) architectures replace traditional bus-based and crossbar interconnects with packet-switched communication networks…
noc router arbitration, noc quality of service, noc topology mesh, noc flow control
Network-on-Chip (NoC) Router Design for SoC is the on-chip communication infrastructure that replaces traditional shared-bus architectures with a packet-switched network…
network-on-chip topology selection and trade-offs, network-on-chip topology selection, topology selection trade-offs, network-on-chip topology, topology selection
Network-on-Chip Topology Selection and Trade-Offs Introduction & Motivation Network-on-Chip Topology Selection and Trade-Offs addresses a central problem in integration process…
nas for accelerators, automl chip design, hardware nas, efficient architecture search
Neural Architecture Search for Hardware is the automated discovery of optimal neural network architectures optimized for specific hardware constraints — where NAS algorithms…
tpu, npu, systolic array, ai chip, hardware ai inference, tensor processing unit
Neural Network Accelerators are the specialized hardware processors designed to perform the matrix multiply-accumulate (MAC) operations that dominate neural network inference…
ml driven rtl generation, ai circuit generation, automated hdl synthesis, learning based logic synthesis
Neural Network Synthesis is the emerging paradigm of using deep learning models to directly generate hardware descriptions, optimize logic circuits, and synthesize chip designs…
chip, architecture, spiking, neural, network, event-driven, brain-inspired
Neuromorphic Chip Architecture is computing architectures mimicking neural biology with asynchronous event-driven computation, spiking neurons, and local learning, enabling…
spiking neural network hardware, intel loihi, ibm truenorth neuromorphic, event driven computing chip
Neuromorphic Chip Architecture is a brain-inspired computing paradigm using spiking neuron circuits and event-driven asynchronous computation to achieve ultra-low power machine…
neuromorphic chip design, neuromorphic chip, chip design
Neuromorphic Chip Design Introduction & Motivation Neuromorphic Chip Design addresses a central problem in hardware-accelerators process control and energy-per-spike-nanojoules…
neuromorphic chip synapse variability prediction, neuromorphic chip synapse, chip synapse variability, synapse variability prediction, neuromorphic chip, chip synapse
Neuromorphic Chip Synapse Variability Prediction with Machine Learning Introduction & Motivation Neuromorphic Chip Synapse Variability Prediction with Machine Learning addresses…
ai accelerators detecting and localizing defects in memristor crossbar arrays used in neuromorphic chips, ai accelerators detecting, accelerators detecting localizing, memristor crossbar arrays
AI Accelerators: Detecting and localizing defects in memristor crossbar arrays used in neuromorphic chips Introduction & Motivation AI Accelerators: Detecting and localizing…
detecting and localizing defects in memristor crossbar arrays used in neuromorphic chips, detecting localizing defects, localizing defects memristor, defects memristor crossbar, crossbar arrays
Detecting and localizing defects in memristor crossbar arrays used in neuromorphic chips Introduction & Motivation Detecting and localizing defects in memristor crossbar arrays…
memristor synaptic device, phase change synaptic, ferroelectric synaptic, spiking device analog
Neuromorphic Semiconductor Devices are specialized hardware substrates implementing brain-inspired computing via memristor/resistive/ferroelectric synaptic elements integrated…
ntd silicon, float zone neutron doping, silicon 30 phosphorus, power device resistivity uniformity, ntd power semiconductor
Neutron transmutation doping, or NTD, turns a silicon wafer into its own dopant source by firing it with a reactor's neutron flux and letting nuclear physics do what no diffusion…
Nikon lithography, precision optics, exposure tool, lithography equipment supplier, wafer scanner
The Nikon stepper refers to the lithography steppers and scanners made by the Japanese optical company Nikon, which became one of the leading suppliers of the exposure machines…
cvd nitride deposition, sinx deposition, si3n4 deposition, deposited silicon nitride, nitride film deposition, semiconductor nitride deposition, low stress silicon nitride, stoichiometric silicon nitride, silicon rich nitride
CVD nitride deposition forms an amorphous silicon–nitrogen-based film whose useful properties depend on composition, hydrogen, density, stress, and interfaces—not merely on…
nitride deposition stress drift prediction, nitride deposition stress, deposition stress drift, stress drift prediction, nitride deposition, deposition stress, stress drift
Nitride Deposition Stress Drift Prediction with Machine Learning Introduction & Motivation Nitride Deposition Stress Drift Prediction with Machine Learning addresses a central…
hard mask semiconductor, silicon nitride mask, poly hard mask, hard mask etch
Hard Mask is a thin inorganic film used as an etch mask in place of or in addition to photoresist — providing superior etch resistance for deep etches, enabling tighter CD…
packaging
Nitrogen purge is the process of replacing ambient air in packaging or process environments with nitrogen to reduce oxygen and moisture exposure - it helps protect sensitive…
packaging
No-clean flux is the flux chemistry formulated to leave minimal benign residue after soldering so post-reflow cleaning is often unnecessary - it is widely used to simplify…
packaging
No-flow underfill is the underfill approach where uncured resin is applied before die placement and cures during solder reflow to combine attach and reinforcement steps - it can…
network on chip qos, traffic class arbitration, noc bandwidth guarantee, latency service level
NoC Quality of Service is the traffic management framework that enforces latency and bandwidth targets on shared on chip networks. What It Covers Core concept: classifies traffic…
metrology
Noise Floor is the minimum signal level below which the instrument cannot distinguish a real signal from noise — defined by the intrinsic noise of the detector, electronics…
packaging
Non-conductive die attach is the die bonding approach using electrically insulating adhesives where conduction is not required through the attach layer - it prioritizes mechanical…
ncf, packaging
Non-conductive film is the pre-applied adhesive film used in chip attach and fine-pitch assembly to provide mechanical bonding and gap fill without conductive particles - it…
metrology
Non-contact measurement is a metrology approach that acquires dimensional, topographic, or material property data without physically touching the sample — essential…
metrology
Non-contact metrology measures a wafer, film, structure, or device without placing a mechanical or electrical probe against the surface. Light, X-rays, electrons, acoustic waves…
XPS surface characterization thin films, chemical state oxidation XPS analysis, depth profiling sputtering XPS, semiconductor interface XPS metrology
X-ray Photoelectron Spectroscopy (XPS): Surface Characterization and Thin Film Analysis in Semiconductor Processing Introduction X-ray photoelectron spectroscopy (XPS), also known…
nuclear reaction analysis, nra, metrology
Nuclear Reaction Analysis (NRA) is an ion beam technique that quantifies light elements (H, D, ³He, Li, B, C, N, O, F) in thin films and at surfaces by bombarding the sample…
metrology
Nuisance defects are detected anomalies that do not actually impact device functionality or yield — false positives from inspection tools that waste review time and resources…
numerical aperture, na, lithography
Numerical Aperture (NA) is the fundamental optical parameter that determines a lithography lens's ability to resolve fine features — defined as NA = n × sin(θ) where n is…
data analysis
Object Detection on Wafers is the application of object detection algorithms to locate and classify multiple defects or features in a single wafer image — predicting both…
boson quantum distribution, bose einstein condensation bec, phonon occupancy lattice thermal conductivity, debye heat capacity, photonic stimulated emission, semiconductor quantum statistics
Bose–Einstein Statistics: Bosonic Occupation Physics, Lattice Phonons, and Photonic Quantum Phenomena in Semiconductors Executive Overview Bose–Einstein (BE) statistics governs…
optical critical dimension, ocd metrology, optical cd measurement, semiconductor ocd
Optical critical-dimension scatterometry infers the average geometry of a periodic semiconductor pattern from how that pattern changes reflected or diffracted light. The tool may…
icp ccp, plasma etch icp ccp, icp plasma etching, ccp plasma etching, inductively coupled plasma, capacitively coupled plasma, oes, optical emission spectroscopy, oes endpoint detection, plasma etch oes, etch endpoint oes
Plasma etching and reactor physics govern the dry, anisotropic material removal processes essential for patterning nanoscale semiconductor features. Driven by radio-frequency…
schottky contact, metal semiconductor contact
Metal-Semiconductor Contacts — the junctions formed where metal interconnects meet semiconductor regions, classified as either ohmic (low resistance) or Schottky (rectifying)…
design
On-chip aging sensors is the embedded monitors that measure degradation-induced performance drift directly on silicon over time - they provide quantitative aging observability…
on-chip bandwidth monitoring and real-time telemetry, on-chip bandwidth monitoring, bandwidth monitoring real-time, monitoring real-time telemetry, on-chip bandwidth, real-time telemetry
On-Chip Bandwidth Monitoring and Real-Time Telemetry Introduction & Motivation On-Chip Bandwidth Monitoring and Real-Time Telemetry addresses a central problem in measurement…
network on chip, noc, on chip bus interconnect, interconnect fabric soc
A network on chip (NoC) is the packet-switched communication fabric that moves data among processors, accelerators, caches, memory controllers, and I/O blocks inside a system on…