contact angle measurement
metrology
Contact Angle Measurement is the metrology technique that quantifies the wettability of a silicon wafer surface by measuring the angle formed at the three-phase contact line where…
360 technical terms and definitions
metrology
Contact Angle Measurement is the metrology technique that quantifies the wettability of a silicon wafer surface by measuring the angle formed at the three-phase contact line where…
metrology
Contact chain is a series of repeated contact holes for resistance testing — long strings of contacts between metal and silicon/poly layers that measure contact resistance…
interconnect predicting contact etch depth uniformity across the wafer, interconnect predicting contact, predicting contact etch, contact etch depth, etch depth uniformity, predicting contact
Interconnect: Predicting contact etch depth uniformity across the wafer Introduction & Motivation Interconnect: Predicting contact etch depth uniformity across the wafer addresses…
contact hole patterning, contact etch, contact resistance, contact fill, contact module, self-aligned contact, SAC, contact plug, MOL contact, lithography
A contact hole is not a shape. It is a vertical electrical path that happens to start as a shape, and the shape is the least interesting thing about it. Every integrated circuit…
metrology
Contact measurement is a metrology approach where a physical probe or stylus touches the sample surface to measure dimensions, topography, or material properties — providing…
specific contact resistance, contact resistivity, salicide contact, metal semiconductor contact, ohmic contact cmos
Self-aligned silicides and nanoscale contact metallization architectures represent the material and thermodynamic interfaces engineered to establish low-resistance ohmic…
contact resistance at metal-semiconductor interface prediction, contact resistance metal-semiconductor, resistance metal-semiconductor interface
Contact Resistance at Metal-Semiconductor Interface Prediction with Machine Learning Introduction & Motivation Contact Resistance at Metal-Semiconductor Interface Prediction…
silicide contact advanced node, metal semiconductor contact, wrap around contact gaa, contact resistivity reduction
Self-aligned silicides and nanoscale contact metallization architectures represent the material and thermodynamic interfaces engineered to establish low-resistance ohmic…
silicide contact, contact scaling, metal semiconductor contact, ohmic contact cmos
Self-aligned silicides and nanoscale contact metallization architectures represent the material and thermodynamic interfaces engineered to establish low-resistance ohmic…
airborne molecular contamination, amc, cleanroom chemistry, contamination sources
Semiconductor cleanroom engineering, ultra-pure water synthesis, and advanced facility distribution networks constitute the critical physical infrastructure required to sustain…
cooling solution design for chiplet stacking and heat extraction, cooling solution design, solution design chiplet, design chiplet stacking, chiplet stacking heat, cooling solution
Cooling Solution Design for Chiplet Stacking and Heat Extraction Introduction & Motivation Cooling Solution Design for Chiplet Stacking and Heat Extraction addresses a central…
coordinate measuring machine, cmm, metrology
Coordinate Measuring Machine (CMM) is a precision 3D measurement system that determines the geometry of physical objects by probing discrete points on their surfaces — used…
packaging
Coplanarity is the degree to which package leads or contact surfaces lie in the same geometric plane - it is a critical parameter for reliable solder-joint formation during board…
cu electroplating, copper plating, damascene plating, copper seed layer, electrochemical deposition, ecd copper
Copper dual damascene interconnect architectures, electrochemical superfilling, and barrier-seed metallization constitute the back-end-of-line (BEOL) wiring systems that route…
Cu ECD, electrochemical deposition, damascene plating
Copper dual damascene interconnect architectures, electrochemical superfilling, and barrier-seed metallization constitute the back-end-of-line (BEOL) wiring systems that route…
electrochemical deposition, ECD copper plating, CMP planarization, BEOL copper interconnect, damascene fill, plating overburden removal
Copper overburden is the excess copper intentionally deposited on top of a wafer's patterned trenches and vias during electrochemical deposition, sitting above the field oxide as…
cu bonding, wire bond, gold wire bonding, forming gas, free air ball, thermosonic bonding, packaging cost reduction, bond pad damage, capillary tooling
Copper wire bonding is a packaging interconnect technique that uses fine copper wire, instead of gold, to connect a chip's bond pads to its package leads — a swap driven almost…
corona charge deposition uniformity prediction machine learning, corona charge, deposition uniformity prediction, corona charge deposition uniformity prediction
Corona Charge Deposition Uniformity Prediction with Machine Learning Introduction & Motivation Corona Charge Deposition Uniformity Prediction with Machine Learning addresses…
metrology
Corona-Kelvin metrology substitutes a controlled deposit of calibrated ionic charge for a conventional metal-oxide-semiconductor (MOS) gate electrode, enabling noncontact…
metrology
Correctables and Residuals in overlay metrology are the two components of the total overlay error — correctables are systematic, repeatable errors that can be modeled and fed back…
metrology
Spectroscopic ellipsometry and inline optical wafer metrology constitute the non-destructive physical measurement and defect detection disciplines that govern yield control across…
semiconductor economics, manufacturing cost, wafer cost, die cost, yield economics, fab economics, hbm4 cost and economics, hbm4 stack cost per bit
Semiconductor Manufacturing Process Cost Modeling Overview Semiconductor cost modeling quantifies the expenses of fabricating integrated circuits—from raw wafer to tested die. It…
industry
Cost per wafer is the total manufacturing cost to process one wafer through all fabrication steps. It's the fundamental unit economics metric for semiconductor manufacturing.…
recycled IC, blacktopping, re-marked chips, AS5553, AS6081, electronic component supply chain fraud
A counterfeit chip is not always a fake die inside a real-looking package — more often, it's a genuine chip that has no business being sold as new, resurfaced, relabeled…
packaging
Cover tape is the sealing film applied over carrier tape pockets to retain components until feeder peel-back at placement - it protects parts during transport while enabling…
metrology
Coverage Factor ( ) is the multiplier applied to the combined standard uncertainty to obtain the expanded uncertainty — , chosen to provide a specified level of confidence…
cowos chip on wafer on substrate, chip-on-wafer-on-substrate, advanced packaging, silicon interposer, hbm packaging
Interposers are the substrates that carry 2.5D integration: a die-to-die wiring layer dense enough to route thousands of connections between chiplets that sit side by side.…
cowos and 3d packaging, cowos packaging, cowos, cowos & emib, cowos and emib, cowos-s, cowos-l, cowos-r, advanced 3d packaging, silicon interposer, 3d hybrid bonding, tsmc cowos
CoWoS & 3D Packaging: Advanced 2.5D/3D Heterogeneous Integration, Sub-Micron Interconnect Physics, and the Packaging Toll Bridge Moat CoWoS (Chip-on-Wafer-on-Substrate) and 3D…
CoWoS, TSMC CoWoS, CoWoS-S, CoWoS-R, CoWoS-L, chip on wafer on substrate
CoWoS technology. is TSMC’s Chip-on-Wafer-on-Substrate family for integrating logic dies, chiplets, and high-bandwidth memory in large 2.5D packages. In the canonical CoWoS-S…
cd-afm, metrology, boot-shaped tip, re-entrant sidewall, tip shape calibration, tip wear, characterization grating, NIST traceable, OCD calibration reference
Critical dimension AFM (CD-AFM) measures the width, height, and sidewall shape of semiconductor features by physically tracing a specially-shaped probe tip across the feature's…
critical dimension, cd, lithography
Critical dimension (CD) is the measurable width of a patterned feature that must be controlled closely because it directly sets the electrical behavior of the device.…
cd metrology sem, cd uniformity across wafer, line width roughness lwr, cd-sem measurement, euv stochastics
Critical Dimension Control Critical dimension (CD) control is the measurement-and-control discipline used to keep patterned feature dimensions within functional limits from mask…
cd-saxs, cdsaxs, critical dimension saxs, cd-saxs metrology, x-ray critical dimension metrology
Critical-dimension small-angle X-ray scattering measures the average three-dimensional shape of periodic semiconductor structures by transmitting short-wavelength X-rays through…
cross-bridge kelvin resistor, cbkr, metrology
Cross-Bridge Kelvin Resistor (CBKR) measures contact resistance accurately — a specialized test structure that separates contact resistance from spreading resistance, enabling…
metrology
Cross-section preparation is the technique of cutting through a semiconductor device perpendicular to the wafer surface to expose its internal layer structure for microscopic…
metrology
Cross-section SEM examines an exposed face through a structure, revealing geometry that a top-down view cannot directly show. A prepared section can reveal layer thicknesses…
cryogenic wafer probe contact prediction, cryogenic wafer probe, wafer probe contact, probe contact prediction, cryogenic wafer, wafer probe, probe contact, contact prediction
Cryogenic Wafer Probe Contact Prediction with Machine Learning Introduction & Motivation Cryogenic Wafer Probe Contact Prediction with Machine Learning addresses a central problem…
point defects, dislocations, stacking faults, bulk defects
Crystal Defects in Semiconductors are deviations from the perfect periodic lattice structure — impacting carrier mobility, leakage current, device reliability, and yield across…
cop defect, vacancy agglomeration silicon, octahedral void silicon, cop silicon wafer, gate oxide cop defect
A crystal-originated particle, or COP, is not contamination at all — it is a tiny octahedral void baked into the silicon itself as the ingot cools, formed when point defects…
cte, packaging
CTE matching with underfill is the material-engineering strategy that selects underfill properties to minimize thermal expansion mismatch between die, bumps, and substrate - it is…
advanced packaging
Copper-to-copper direct bonding joins two metal surfaces into a single continuous conductor without solder, adhesive or any intermediate phase. In advanced packaging it appears as…
copper to copper direct bonding, dbi direct bond interconnect, bumpless 3d packaging, wafer to wafer bonding alignment, hybrid bonding overlay accuracy, hbm4 hybrid bonding, hbm4 die to die bonding
Hybrid bonding joins two wafers or dies by bonding copper pads and the surrounding dielectric at the same time, producing a metallurgical copper-to-copper connection with no…
packaging
Cull is the residual molding compound left in the pot and transfer channels after cavity filling in transfer molding - it is non-product material that affects both process…
packaging
Cure time is the duration required for molding compound to achieve sufficient crosslinking and mechanical integrity in the mold - it governs package strength, residual stress…
curvilinear opc, inverse lithography curvilinear, multi beam mask writing opc, continuous mask synthesis
Curvilinear Mask Optimization — also designated as Curvilinear OPC, Continuous ILT Mask Synthesis, or Non-Manhattan Mask Optimization — is the advanced computational lithography…
lithography
Curvilinear Masks are photomasks containing non-Manhattan (curved and diagonal) shape contours computationally generated by inverse lithography technology to achieve maximum…
chemical vapor deposition, cvd process
Chemical vapor deposition is the semiconductor workhorse for growing thin, conformal films from gaseous precursors on a heated wafer surface. In a CVD process, reactant gases flow…
cvd, chemical vapor deposition chamber, cvd reactor, deposition chamber, pecvd chamber, thin film reactor, cvd equipment
A CVD chamber is a reactor with memory: source delivery, injector conductance, pressure control, wafer temperature, plasma state, surface kinetics, wall coating, clean and season…
cvd equipment, cvd reactor, lpcvd, pecvd, mocvd, cvd chamber modeling, cvd process modeling, chemical vapor deposition equipment, cvd reactor design, cvd simulation, cvd transport phenomena, cvd feature scale
CVD equipment modeling translates the geometry, materials, and operating conditions of a chemical vapor deposition reactor into coupled transport and chemistry equations whose…
chemical vapor deposition, cvd process, lpcvd, pecvd, hdp-cvd, mocvd, ald, thin film deposition, cvd equipment, cvd simulation
CVD modeling turns a deposition recipe into a testable chain of conservation laws, chemical mechanisms, surface boundary conditions, and scale-bridging assumptions, so its purpose…