1,016 technical terms and definitions
double-sided cooling power module prediction, double-sided cooling power, cooling power module, power module prediction, double-sided cooling, cooling power, power module
Double-Sided Cooling Power Module Prediction with Machine Learning Introduction & Motivation Double-Sided Cooling Power Module Prediction with Machine Learning addresses a central…
double spending prevention, double spending, spending prevention
Double Spending Prevention Introduction & Motivation Double Spending Prevention addresses a central problem in blockchain process control and confirmation-requirement-depth…
Augmented Inverse Probability Weighting AIPW Introduction & Motivation Augmented Inverse Probability Weighting AIPW addresses a central problem in causal inference and {target}…
Doubly Robust Estimation Introduction & Motivation Doubly Robust Estimation addresses a central problem in estimating causal effects with causalml methods: how to Estimate…
Doubly Robust Causal Estimation Introduction & Motivation Doubly Robust Causal Estimation addresses a central problem in causal inference and {target} analysis: how to Apply…
Doubly Robust Estimation (Extended Study) Introduction & Motivation Doubly Robust Estimation (Extended Study) addresses a central problem in estimating causal effects…
Doubly Robust Estimation (Extended Study) Introduction & Motivation Doubly Robust Estimation (Extended Study) addresses a central problem in estimating causal effects…
Doubly Robust Estimation (Extended Study) Introduction & Motivation Doubly Robust Estimation (Extended Study) addresses a central problem in estimating causal effects…
downstream asher strip rate uniformity prediction machine learning, downstream asher, strip rate uniformity, downstream asher strip rate uniformity prediction
Downstream Asher Strip Rate Uniformity Prediction with Machine Learning Introduction & Motivation Downstream Asher Strip Rate Uniformity Prediction with Machine Learning addresses…
downstream plasma asher chamber wall deposit prediction machine learning, downstream plasma, asher chamber wall, downstream plasma asher, plasma asher chamber
Downstream Plasma Asher Chamber Wall Deposit Prediction with Machine Learning Introduction & Motivation Downstream Plasma Asher Chamber Wall Deposit Prediction with Machine…
dp-sgd, training techniques
DP-SGD is differentially private stochastic gradient descent that clips per-example gradients and adds calibrated noise - It is a core method in modern semiconductor AI serving…
diffusion sampler, stable diffusion
DPM++ (Diffusion Probabilistic Model++) is an advanced sampling method for diffusion models — generating high-quality images in fewer steps than DDPM through improved ODE solvers…
generative models
DPM-Solver is a family of high-order ODE solvers specifically designed for the probability flow ODE of diffusion models, providing faster and more accurate sampling than generic…
generative models
DPM-Solver is the family of high-order numerical solvers for diffusion ODEs that attains strong quality with very few model evaluations - it is one of the most effective…
DRAEM Discriminative Reconstruction Embedding for Defects Introduction & Motivation DRAEM Discriminative Reconstruction Embedding for Defects addresses a central problem…
optimization
Draft Model is the fast proposal model used in speculative decoding to generate candidate tokens - It is a core method in modern semiconductor AI serving…
inference
Draft model selection is the process of choosing the proposer model used in speculative decoding to maximize acceptance rate and net speedup under quality constraints - selection…
dragonfly algorithm navigation, dragonfly algorithm, algorithm navigation
Dragonfly Algorithm Navigation Introduction & Motivation Dragonfly Algorithm Navigation addresses a central problem in ml process control and path-quality-optimization prediction…
Dragonnet Targeted Regularization for CATE Estimation Introduction & Motivation Dragonnet Targeted Regularization for CATE Estimation addresses a central problem in causal…
drain-induced barrier lowering prediction, drain-induced barrier lowering, barrier lowering prediction, drain-induced barrier, barrier lowering, lowering prediction
Drain-Induced Barrier Lowering Prediction with Machine Learning Introduction & Motivation Drain-Induced Barrier Lowering Prediction with Machine Learning addresses a central…
drain-induced barrier lowering prediction, drain-induced barrier lowering, barrier lowering prediction, drain-induced barrier, barrier lowering, lowering prediction
Drain-Induced Barrier Lowering Prediction with Machine Learning Introduction & Motivation Drain-Induced Barrier Lowering Prediction with Machine Learning addresses a central…
ibm dennard 1t1c write wait read retention test, 1t1c dram weakest cell retention distribution guard band, dram 1968 refresh interval protects stored charge margin
Measure the Retention Time and Set the Refresh Interval 1. Retention Time Is Measured from a Completed Write to the Last Reliable Read Step 5 established that leakage continuously…
ibm dennard 1t1c cell density shared array overhead, 1t1c dram refresh occupancy sensing restore tradeoff, dram 1968 qualify complete memory macro architecture
Qualify the Trade: Density Against Refresh Complexity 1. The Cell Becomes Simpler by Moving Work into the Array The 1T1C architecture does not eliminate the functions a memory…
compute the economics this architecture actually displaced cost per, compute cost per bit against magnetic core
Compute the Economics This Architecture Actually Displaced: Cost Per Bit Against Magnetic Core Step 8 measured area advantage in device terms; the commercial argument that…
establish how the industry actually licensed dennards 1968 claim, establish cross licensing around the 1968 patent
Establish How the Industry Actually Licensed Dennard's 1968 Claim A patented architecture that the patent-holder's own company does not exclusively commercialize (Step 14) raises…
model wafer scale yield for an array built from, model wafer scale yield for a repeated
Model Wafer-Scale Yield for an Array Built From One Repeated Cell Step 9 qualified density against refresh complexity at the architecture level; manufacturing this array at volume…
dram capacitor aspect ratio uniformity prediction, dram capacitor aspect, capacitor aspect ratio, aspect ratio uniformity, ratio uniformity prediction, aspect ratio
DRAM Capacitor Aspect Ratio Uniformity Prediction with Machine Learning Introduction & Motivation DRAM Capacitor Aspect Ratio Uniformity Prediction with Machine Learning addresses…
dram capacitor dielectric leakage current prediction, dram capacitor dielectric, capacitor dielectric leakage, dielectric leakage current, dram capacitor
DRAM Capacitor Dielectric Leakage Current Prediction with Machine Learning Introduction & Motivation DRAM Capacitor Dielectric Leakage Current Prediction with Machine Learning…
dram capacitor leakage drift prediction, dram capacitor leakage, capacitor leakage drift, leakage drift prediction, dram capacitor, capacitor leakage, leakage drift, drift prediction
DRAM Capacitor Leakage Drift Prediction with Machine Learning Introduction & Motivation DRAM Capacitor Leakage Drift Prediction with Machine Learning addresses a central problem…
dram refresh bitmap repair prediction, dram refresh bitmap, refresh bitmap repair, bitmap repair prediction, dram refresh, refresh bitmap, bitmap repair, repair prediction
DRAM Refresh Bitmap Repair Prediction with Machine Learning Introduction & Motivation DRAM Refresh Bitmap Repair Prediction with Machine Learning addresses a central problem…
dram refresh command overhead prediction, dram refresh command, refresh command overhead, command overhead prediction, dram refresh, refresh command, command overhead
DRAM Refresh Command Overhead Prediction with Machine Learning Introduction & Motivation DRAM Refresh Command Overhead Prediction with Machine Learning addresses a central problem…
dram refresh cycle optimization prediction, dram refresh cycle, refresh cycle optimization, cycle optimization prediction, dram refresh, refresh cycle, cycle optimization
DRAM Refresh Cycle Optimization Prediction with Machine Learning Introduction & Motivation DRAM Refresh Cycle Optimization Prediction with Machine Learning addresses a central…
dram refresh interval drift prediction, dram refresh interval, refresh interval drift, interval drift prediction, dram refresh, refresh interval, interval drift, drift prediction
DRAM Refresh Interval Drift Prediction with Machine Learning Introduction & Motivation DRAM Refresh Interval Drift Prediction with Machine Learning addresses a central problem…
dram refresh overhead and capacity trade-offs, dram refresh overhead, refresh overhead capacity, overhead capacity trade-offs, dram refresh, refresh overhead, overhead capacity
DRAM Refresh Overhead and Capacity Trade-Offs Introduction & Motivation DRAM Refresh Overhead and Capacity Trade-Offs addresses a central problem in memory process control…
dram refresh rate optimization, dram refresh rate, refresh rate optimization, dram refresh, refresh rate, rate optimization
DRAM Refresh Rate Optimization with Machine Learning Introduction & Motivation DRAM Refresh Rate Optimization with Machine Learning addresses a central problem in DRAM refresh…
dram memory optimizing refresh rates in dram to balance power and data retention, dram memory optimizing, memory optimizing refresh, optimizing refresh rates, refresh rates dram, dram memory
DRAM Memory: Optimizing refresh rates in DRAM to balance power and data retention Introduction & Motivation DRAM Memory: Optimizing refresh rates in DRAM to balance power and data…
optimizing refresh rates in dram to balance power and data retention, optimizing refresh rates, refresh rates dram, rates dram to, dram to balance, to balance power, balance power data
Optimizing refresh rates in DRAM to balance power and data retention Introduction & Motivation Optimizing refresh rates in DRAM to balance power and data retention addresses…
dram refresh row hammer prediction, dram refresh row, refresh row hammer, row hammer prediction, dram refresh, refresh row, row hammer, hammer prediction
DRAM Refresh Row Hammer Prediction with Machine Learning Introduction & Motivation DRAM Refresh Row Hammer Prediction with Machine Learning addresses a central problem in DRAM…
next-generation dram technology, next-generation dram, dram technology
Next-Generation DRAM Technology Introduction & Motivation Next-Generation DRAM Technology addresses a central problem in memory process control and capacity-per-die prediction…
dram storage capacitor aspect ratio prediction machine learning, dram storage, capacitor aspect ratio, dram sem, dram storage capacitor aspect ratio prediction
DRAM Storage Capacitor Aspect Ratio Prediction with Machine Learning Introduction & Motivation DRAM Storage Capacitor Aspect Ratio Prediction with Machine Learning addresses…
dram technology roadmap, dram technology, technology roadmap
DRAM Technology Roadmap Introduction & Motivation DRAM Technology Roadmap addresses a central problem in memory process control and capacity prediction: how to Predict capacity…
dram voltage and timing drift prediction, dram voltage timing, voltage timing drift, timing drift prediction, dram voltage, voltage timing, timing drift, drift prediction
DRAM Voltage and Timing Drift Prediction with Machine Learning Introduction & Motivation DRAM Voltage and Timing Drift Prediction with Machine Learning addresses a central problem…
dram word line resistance variation prediction, dram word line, word line resistance, line resistance variation, resistance variation prediction, dram word, word line
DRAM Word Line Resistance Variation Prediction with Machine Learning Introduction & Motivation DRAM Word Line Resistance Variation Prediction with Machine Learning addresses…
ti tms4030, dram4k 1973
Detail the MK4096 Pinout and Packaging The MK4096 packed power, ground, six multiplexed address pins, data in, data out, chip select, and the RAS and CAS control pins into…
ras cas multiplexing, dram4k 1973
Detail MK4096 Timing Specifications Because row and column addresses now arrived sequentially rather than simultaneously, the MK4096's datasheet specified exact timing windows…
row address strobe column address strobe active low latch, t_rcd ras to cas delay sense amplifier settling time, ras cas timing cost traded against pin count savings
Tell the Chip Which Half of the Address It Is Looking At 1. Add the Signal the Multiplexing Scheme Was Missing Step 1 showed that the same 8 pins can carry a row address and then…
multiplexed addressing architecture outlives specific numbers, pin count constraint propagated never resolved away, first dram series about periphery not cell interior
Classify and Close: What Every Later DRAM Keeps, and What Was Only 64K's Own Arithmetic 1. Separate the Enduring Mechanism From This Generation's Particular Numbers Every step…
trench dram keyhole void pinch off knudsen diffusion limit, conformal lpcvd dielectric and polysilicon trench fill dram, step coverage aspect ratio dependent deposition dram yield
Step 7 — Fill the Trench Without Leaving a Void: Conformal Deposition and the Pinch-Off Limit 1. Knudsen Diffusion and the Threat of Premature Pinch-Off Once a high-aspect-ratio…
dennard scaling breakdown 3d capacitor evolution dram, trench vs stacked legacy 3d semiconductor architecture dram, when planar physics failed 3d dimension solved moore law
Step 10 — The 1974 Retrospective: When Leaving the Plane Became the Only Way Forward 1. The Immutable Circuit Law and the Collapse of Two Dimensions Robert Dennard’s 1968 1T1C…
texture the stacked capacitors own surface hemispherical grain polysilicon, texture stacked capacitor surfaces with hemispherical grain
Texture the Stacked Capacitor's Own Surface: Hemispherical-Grain Polysilicon Step 15 named high-permittivity dielectrics as one lever beyond pure geometry; the stacked path also…