via etch

# Via Etch (V1)

Via etching opens an insulating layer to connect wiring levels. V1 often denotes the via between M1 and M2, subject to the layer map.

## Follow the transitions

Each box marks a manufacturing purpose, not an executable recipe. Some integrations combine steps or move strip and clean operations. Endpoint, where used, must be qualified against feature clearing and underlayer loss.

## Integration context

The landing may be a conductor or an etch-stop cap requiring a separate opening. A contact to a device and a via between metals have different exposure and damage concerns. Dual-damascene integrations coordinate via and trench patterning rather than follow one universal sequence.

## What to verify

Verify landing integrity, bottom residue and electrical via resistance.

Define the input surface and the acceptance criterion at each transition. A qualified transition must account for pattern density, wafer position and incoming-film variation; a nominal clearing time on one monitor does not establish the full operating window.

## Related terminology

via etch, V1 etch, via etch process flow, V1. Short abbreviations are local process vocabulary and can have other meanings; use the full module name when searching.

## Source and scope

[Reactive ion etching capabilities](https://www.nanofab.ualberta.ca/capabilities/plasma-etch/). The diagram is an original teaching schematic. Layer choices and process families describe an example rather than a universal manufacturing recipe.