tunnel fet

# Tunnel Field-Effect Transistor (TFET) Fabrication, Band-to-Band Tunneling & Heterojunction Scaling

In conventional metal-oxide-semiconductor field-effect transistors (MOSFETs), carrier injection from the source into the channel occurs via thermionic emission over an electrostatic potential barrier. Because carriers in the source conform to Fermi-Dirac statistics, the distribution of high-energy carriers exhibits an exponential Boltzmann tail:

f(E) \propto \exp\left( -\frac{E - E_F}{k_B T} \right)

This fundamental physical law imposes an immutable thermodynamic floor on the subthreshold swing (SS) of any thermionic transistor at room temperature (T = 300\,\text{K}), widely termed the Boltzmann Tyranny:

SS = \left( \frac{\partial \log_{10} I_D}{\partial V_{gs}} \right)^{-1} = \ln(10) \frac{k_B T}{q} \left( 1 + \frac{C_{dep}}{C_{ox}} \right) \ge \mathbf{60\,\text{mV/decade at } 300\,\text{K}}

Because the subthreshold slope cannot be steeper than 60\,\text{mV/dec}, scaling the power supply voltage below V_{dd} \approx 0.7\,\text{V} in advanced logic chips leads to exponential surges in OFF-state leakage current (I_{off}), stalling supply voltage scaling.

The Tunnel Field-Effect Transistor (TFET) breaks the Boltzmann Tyranny by replacing thermionic emission with quantum-mechanical Band-to-Band Tunneling (BTBT) through a reverse-biased p^+-i-n^+ junction. The semiconductor bandgap acts as an energetic high-pass filter that truncates the Maxwell-Boltzmann thermal tail, enabling sub-thermal switching with SS < 60\,\text{mV/decade} (experimentally demonstrated at 30\text{ to }40\,\text{mV/dec}). This steep switching behavior permits supply voltage scaling down to V_{dd} \approx 0.2\text{ to }0.3\,\text{V}, reducing dynamic switching power by > 80\% for ultra-low-power edge computing, cryogenic processors, and biomedical electronics.

Thermionic Emission vs. Band-to-Band Tunneling (TFET) breaking the 60 mV/decade Boltzmann Tyranny via quantum energy filtering 1. THERMIONIC EMISSION (MOSFET) Source (n⁺) Barrier: qψ_B Drain (n⁺) Boltzmann Tail e^(-E/k_BT) Thermal Diffusion Over Barrier Boltzmann Thermodynamic Limit: SS = ln(10) · (k_B T / q) · (1 + C_dep/C_ox) ≥ 60 mV/dec • At T = 300 K, ln(10) · (k_B T / q) ≈ 59.6 mV/decade. • Energetic electrons in the Fermi tail spill over the barrier even in the OFF state, creating static leakage. Scaling Roadblock: • Lowering V_dd below 0.7 V requires lowering V_th. • Because SS ≥ 60 mV/dec, I_off increases by 10× for every 60 mV reduction in V_th! • Standby power explodes, stalling CMOS voltage scaling. 2. BAND-TO-BAND TUNNELING (TFET) E_C E_V Source (p⁺) Channel (i) Drain (n⁺) Tunneling Window BTBT Vector → Width d_tunnel Quantum Mechanical Filtering: SS_eff < 60 mV/decade at 300 K (Sub-Thermal) • Valence band in source acts as an energetic high-pass filter. • Electrons below E_V cannot tunnel because there are no available states in the channel bandgap (E_g,channel). Ultra-Low Voltage Operation: • Enables steep switching with average SS ≈ 35–40 mV/dec. • Allows V_dd scaling down to 0.20 V – 0.30 V. • Dynamic switching energy E_dyn = C · V_dd² drops by > 80% • Prime technology for always-on edge AI and biomedical devices.

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## 1. Band-to-Band Tunneling Physics: WKB Approximation & Kane's Model

Carrier transport in a Tunnel FET is governed by quantum-mechanical tunneling across the electrostatic potential barrier formed between the degenerate p^+-type source and the gate-controlled intrinsic channel.

### 1.1 Wentzel-Kramers-Brillouin (WKB) Tunneling Probability
Approximating the tunneling junction as a triangular barrier of effective bandgap E_{g,eff} and junction electric field \mathcal{E}, the tunneling transmission probability T_{WKB} derived from the WKB approximation is:

T_{WKB} \approx \exp\left( -\frac{4 \sqrt{2 m^*} E_{g,eff}^{3/2}}{3 q \hbar \mathcal{E}} \right)

Where:
- m^* = (m_e^* m_h^*) / (m_e^* + m_h^*) is the reduced carrier tunneling effective mass.
- E_{g,eff} is the effective tunneling energy barrier across the junction.
- \mathcal{E} is the screening electric field perpendicular to the hetero-interface.
- \hbar = h / (2\pi) is the reduced Planck constant.

### 1.2 Kane's Band-to-Band Tunneling Model
The volume generation rate of tunnel carriers G_{BTBT} is given by Kane's analytical formulation:

G_{BTBT} = A \cdot \mathcal{E}^2 \exp\left( -\frac{B}{\mathcal{E}} \right)

Where the tunneling prefactor A and exponential factor B are material-dependent constants:

A = \frac{q^2 \sqrt{m^*}}{2 \pi^3 \hbar^2 \sqrt{E_{g,eff}}}, \qquad B = \frac{\pi \sqrt{m^*} E_{g,eff}^{3/2}}{2 \sqrt{2} q \hbar}

The drain current I_D is proportional to the integral of G_{BTBT} over the tunneling volume where the valence band of the source overlaps in energy with the conduction band of the channel (\Delta \Phi = E_{V,source} - E_{C,channel} > 0):

I_D = q \int_{V} G_{BTBT} \, dV

Heterojunction Band Alignments & Transfer Scaling homojunction vs. staggered Type-II vs. broken-gap Type-III tunneling kinetics HETEROJUNCTION BAND ENGINEERING 1. Silicon Homojunction (E_g = 1.12 eV, Indirect) • Phonon-assisted tunneling required (indirect bandgap). • Large tunneling width d_tunnel > 8 nm ⟹ massive B factor. • Severely degraded drive current: I_on < 0.1 μA/μm (Unusable for logic). 2. Type-II Staggered (InGaAs / GaAsSb) • Direct bandgap direct tunneling (no phonon assistance). • Effective barrier E_g,eff ≈ 0.35 eV ⟹ d_tunnel ≈ 2.5 nm. • Drive current boosted: I_on ≈ 50–150 μA/μm at V_dd = 0.3 V. 3. Type-III Broken-Gap (InAs / GaSb) • InAs E_C sits below GaSb E_V (negative or near-zero barrier!). • Tunneling width d_tunnel < 1.5 nm ⟹ ultra-high transmission. • Exceptional drive current: I_on > 350 μA/μm with steep SS. • Requires careful gate overlap to suppress OFF-state leakage. I_d–V_gs & DYNAMIC POWER COMPARISON V_gs (V) log I_d MOSFET (V_dd=0.7V) TFET (V_dd=0.3V) Ambipolar SS ≥ 60 SS = 38 mV/dec Dynamic Energy Scaling Law: E_dynamic = C_load · V_dd² Quantitative Power Reduction: • MOSFET: V_dd = 0.70 V ⟹ E_dyn ∝ (0.70)² = 0.490 aJ/fF • TFET: V_dd = 0.25 V ⟹ E_dyn ∝ (0.25)² = 0.0625 aJ/fF • Net Dynamic Energy Savings: 87.2% reduction! Ambipolar Suppression Technique: • Gate underlap at drain + asymmetric lightly doped drain (n⁻) completely quenches parasitic drain-channel tunneling.

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## 2. The Drive Current Bottleneck: Why Silicon Homojunctions Fail

The primary limitation of first-generation silicon homojunction TFETs is extremely low ON-state drive current (I_{on} < 0.1\,\mu\text{A}/\mu\text{m}, compared to \sim 1000\,\mu\text{A}/\mu\text{m} in MOSFETs).

This deficiency stems directly from the exponential factor B in Kane's model:

B = \frac{\pi \sqrt{m^*} E_{g,eff}^{3/2}}{2 \sqrt{2} q \hbar}

1. Large Indirect Bandgap (E_g = 1.12\,\text{eV}): Silicon's large bandgap enters B to the 3/2 power (E_g^{3/2} = 1.186\,\text{eV}^{3/2}).
2. Phonon Assistance Requirement: Because silicon has an indirect bandgap, band-to-band tunneling requires simultaneous absorption or emission of a transverse acoustic (TA) or transverse optical (TO) phonon to satisfy momentum conservation (\Delta k \ne 0). This second-order quantum process suppresses tunneling probability by over three orders of magnitude relative to direct bandgap materials.
3. Large Tunneling Distance (d_{tunnel} > 8\,\text{nm}): The physical distance an electron must tunnel through forbidden energy space exceeds 8\,\text{nm}, driving T_{WKB} < 10^{-6}.

To achieve logic-competitive drive currents (I_{on} > 200\text{ to }500\,\mu\text{A}/\mu\text{m}) while maintaining sub-thermal subthreshold slope, device architects turn to heterojunction engineering.

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## 3. Heterojunction Engineering: Staggered (Type-II) & Broken-Gap (Type-III)

By combining materials with differing band alignments at the tunneling interface, the effective bandgap E_{g,eff} is decoupled from the bulk bandgaps:

### 3.1 Type-II Staggered Heterojunctions
In a staggered alignment (e.g., p-type \text{GaAs}_{0.5}\text{Sb}_{0.5} source with n-type \text{In}_{0.53}\text{Ga}_{0.47}\text{As} channel, lattice-matched to \text{InP}):
- The valence band of GaAsSb sits just below the conduction band of InGaAs.
- Effective tunneling barrier:
E_{g,eff} = E_{C,InGaAs} - E_{V,GaAsSb} \approx \mathbf{0.30\text{ to }0.45\,\text{eV}}
- The tunneling barrier width shrinks from 8\,\text{nm} down to 2.5\,\text{nm}.
- Both semiconductors have direct bandgaps, eliminating the requirement for phonon assistance.
- Achieves drive currents of I_{on} \approx 100\text{ to }200\,\mu\text{A}/\mu\text{m} at V_{dd} = 0.3\,\text{V}.

### 3.2 Type-III Broken-Gap Heterojunctions
In a broken-gap alignment (e.g., p-type \text{GaSb} source with n-type \text{InAs} channel):
- The valence band edge of GaSb lies above the conduction band edge of InAs:
E_{V,GaSb} - E_{C,InAs} \approx \mathbf{+0.15\,\text{eV}}
- The effective tunneling barrier vanishes (E_{g,eff} \le 0), turning the junction into an ultra-transparent Esaki diode.
- The tunneling width is determined strictly by the thickness of the electrostatic screening layer (d_{tunnel} < 1.5\,\text{nm}).
- Tunneling transmission approaches unity (T_{WKB} \to 1), delivering drive currents exceeding:
I_{on} > \mathbf{350\text{ to }500\,\mu\text{A}/\mu\text{m at } V_{dd} = 0.3\,\text{V}}

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## 4. Nanofabrication Architecture: Gate-All-Around & Ambipolarity Suppression

Realizing steep-switching TFETs requires tight electrostatic control and the suppression of parasitic transport mechanisms:

### 4.1 Gate-All-Around (GAA) Nanowire Geometry
To maximize the junction electric field \mathcal{E} for a given gate overdrive, TFETs are implemented as Gate-All-Around (GAA) nanowires or nanosheets. The natural electrostatic scaling length in a cylindrical GAA structure is:

\lambda_{cyl} = \sqrt{\frac{2 \epsilon_{ch} d_{wire}^2 \ln\left(1 + \frac{2 t_{ox}}{d_{wire}}\right) + \epsilon_{ox} d_{wire}^2}{8 \epsilon_{ox}}}

Using nanowire diameters d_{wire} \le 6\text{ to }8\,\text{nm} and high-k dielectric \text{HfO}_2 (EOT < 0.8\,\text{nm}), \lambda_{cyl} is compressed below 2\,\text{nm}. This ultra-steep electrostatic potential transition maximizes the junction field \mathcal{E} > 3\,\text{MV/cm}, opening the tunneling window abruptly.

### 4.2 Ambipolar Conduction Suppression
Because a TFET has an asymmetric p^+-i-n^+ structure, applying a negative gate voltage (V_{gs} \ll 0) pulls the channel valence band above the drain conduction band (E_{V,channel} > E_{C,drain}). This triggers parasitic band-to-band tunneling at the channel-drain interface, causing unwanted drain current to surge at negative bias (ambipolar branch).

Foundries suppress ambipolar conduction using two structural modifications:
1. Asymmetric Drain Underlap: Spacing the gate electrode away from the drain contact edge by an un-gated spacer distance (L_{underlap} \approx 10\text{ to }15\,\text{nm}).
2. Lightly Doped Drain (n^-): Lowering the drain doping concentration to N_D \le 1 \times 10^{18}\,\text{cm}^{-3}. This widens the channel-drain depletion barrier to > 15\,\text{nm}, quenching parasitic tunneling and suppressing ambipolar leakage below I_{ambipolar} < 10^{-14}\,\text{A}/\mu\text{m}.

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## 5. Technology Trade-Offs & Application Domains

+----------------------------------------------------------------------------------------------------+
|                                    TFET VS. CONVENTIONAL MOSFET TRADE-OFF MATRIX                   |
+--------------------+--------------------+--------------------+-------------------------------------+
| PERFORMANCE METRIC | CONVENTIONAL MOSFET (GAA / FINFET)      | HETEROJUNCTION TFET (TYPE-II/III)   |
+--------------------+--------------------+--------------------+-------------------------------------+
| Subthreshold Swing | Thermally limited: SS ≥ 60 mV/dec       | Sub-thermal: SS ≈ 35–45 mV/dec      |
| Supply Voltage     | Minimum V_dd ≈ 0.65 to 0.75 V           | Scaled V_dd ≈ 0.20 to 0.35 V        |
| Dynamic Energy     | Baseline: E_dyn ∝ (0.7 V)² ≈ 0.49 aJ/fF | Ultra-low: E_dyn ∝ (0.25 V)² ≈ 0.06 |
|                    |                                         | (> 80% dynamic energy reduction!)   |
| Peak Drive Current | High: I_on ≈ 1000–1500 μA/μm            | Moderate: I_on ≈ 200–500 μA/μm      |
| Operating Speed    | High frequency (> 3 to 5 GHz)           | Moderate frequency (< 1 to 2 GHz)   |
| Primary Domain     | High-Performance Computing (HPC / AI)   | Ultra-Low-Power Edge / IoT / Medical|
+--------------------+--------------------+--------------------+-------------------------------------+

While conventional MOSFETs remain superior for peak clock frequencies in high-performance datacenter compute, Heterojunction TFETs are the premier device architecture for energy-constrained environments—including battery-less energy-harvesting IoT nodes, implantable medical sensors, and always-on smart vision processors—where operation at V_{dd} \le 0.3\,\text{V} delivers up to an order-of-magnitude reduction in total energy consumption.

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