static-power

Static power is the portion of a chip's total power consumption that a transistor burns continuously, even while it's fully switched off and nothing on the chip is actively toggling — the direct counterpart to dynamic power, which exists only during active switching. Static power comes almost entirely from leakage current, small but genuinely nonzero currents that sneak through a transistor even in its supposedly nonconducting state, and because every single transistor on a chip leaks at least a little regardless of whether it's doing any useful work at that instant, static power scales directly with transistor count rather than with how much actual switching activity is happening. How static power actually accumulates across billions of transistors, whether they're working or sitting idle, looks like this:

A few things are worth knowing about why leakage, once a minor footnote in chip power budgets, became one of the central engineering problems in modern process technology:

Subthreshold leakage, the dominant source of static power, exists because a real transistor's conduction doesn't actually switch off abruptly at its threshold voltage — it tapers off exponentially instead, meaning some current always sneaks through even when the gate voltage sits comfortably below threshold. A transistor's "off" state is an idealization; the real current-versus-gate-voltage relationship follows a smooth exponential curve, not a hard cutoff, so even a gate voltage well into the supposedly nonconducting region still permits a small but genuinely nonzero current to flow continuously. This exponential relationship is precisely why subthreshold leakage is so sensitive to small changes in threshold voltage — a chip has no way to make this leakage reach literally zero, only engineer it down to an acceptably small, manageable level, because the underlying physics never actually produces a true, complete off state.

Threshold voltage and leakage are locked in a direct, unavoidable tradeoff, because lowering a transistor's threshold voltage to switch faster at a given supply voltage simultaneously raises that same transistor's subthreshold leakage exponentially, meaning the same design choice that helps performance directly hurts static power. A lower threshold voltage means a transistor needs less gate voltage overdrive to turn on strongly, which helps it switch faster and lets a chip run at lower supply voltages for better dynamic-power efficiency — but because subthreshold conduction follows an exponential relationship with how far the gate voltage sits below threshold, even a small reduction in threshold voltage produces a disproportionately large increase in how much current leaks through while nominally off. This genuine, unavoidable tension between threshold voltage, switching speed, and leakage is exactly why process technology offers multiple transistor threshold-voltage flavors on the same chip, letting designers deliberately choose faster, leakier transistors for speed-critical paths and slower, lower-leakage transistors everywhere speed matters less.

Static power's share of total chip power has grown dramatically as transistors have shrunk across successive process generations, to the point where leakage, once a minor footnote in a chip's overall power budget, is now a first-order design concern engineers spend enormous effort actively managing. Shrinking a transistor generally means a thinner gate oxide and a shorter channel, and both of those geometric changes independently tend to increase leakage through additional mechanisms layered on top of ordinary subthreshold conduction — a thinner oxide permits more gate leakage current tunneling directly through the insulator, and a shorter channel is more susceptible to additional leakage paths opening up between source and drain. This is exactly why static power management evolved from a minor afterthought in older process generations into one of the central engineering challenges of modern chip design, driving the development of entire families of leakage-reduction techniques that simply weren't necessary, or even particularly relevant, at older, larger process nodes.

Power gating, which physically disconnects an entire unused block from the supply rail using a dedicated switch transistor, is the technique that actually addresses static power directly, in a way that clock gating — effective against dynamic power — fundamentally cannot touch. Clock gating stops a block's flip-flops from switching by blocking the clock signal, which genuinely eliminates that block's dynamic power, but every transistor in that block is still fully connected to the supply rail and still leaking current continuously regardless of whether the clock reaches it — clock gating simply has no effect on static power at all. Power gating instead inserts a switch transistor, commonly called a sleep transistor, between the block and its supply rail, genuinely cutting off the supply current path entirely when that block isn't needed, which is the only way to meaningfully reduce the static power an idle block contributes, at the real cost of needing time and energy to ramp the block's supply voltage back up before it can resume useful work.

Read static power as the unavoidable cost of simply having transistors connected to a supply rail, not a secondary concern alongside dynamic power: it comes almost entirely from leakage current that real transistor physics can never reduce to literally zero, it scales with transistor count rather than switching activity, and its direct tradeoff against threshold voltage and transistor speed is exactly why modern chips need both clock gating and power gating as genuinely separate, complementary techniques — one that can only ever address dynamic power, and another that's the sole real tool against static power's continuous, always-on cost.