soic

SoIC — System on Integrated Chips — is TSMC's own brand name for its chip-stacking technology family within the 3DFabric advanced-integration portfolio, used to bond separately fabricated chiplets together through dense, short chip-to-chip connections, and it names a stacking technology, not a transistor process node. The acronym also has an unrelated established meaning in conventional packaging — small-outline integrated circuit, a leaded surface-mount package — so writing out "TSMC SoIC" resolves the ambiguity. How a TSMC SoIC stack gets built, and where it sits in a larger finished package, looks like this:

System partitioned
Logic, cache, or other functions split across chiplets
High-traffic functions placed
Chosen for short-link proximity
Stacking and bondingDense vertical connections, not conventional solder microbumps
Dies prepared for bonding
Hybrid or direct bonding, avoiding microbump pitch limits
Stack assembled
Short vertical links between dies
Power and thermal managed
Stacking raises power density, obstructs heat paths
Known-good-die screening
Before and after stacking
↻ next product generation
SoIC stack integrated into larger package
Alongside interposer, memory, additional dies

A few things are worth knowing about why SoIC names one layer of the integration hierarchy, not the whole package:

Dense, short connections are the mechanism SoIC uses to recover some of monolithic chip's communication benefits while still partitioning across separate dies. Hybrid or direct bonding can place logic, cache, or other functions close together with far more connections per unit area than conventional solder microbumps allow in relevant implementations, which can reduce communication energy and raise connection density — but the benefit actually realized depends on how the system is partitioned and where the traffic-heavy functions are placed, not on the bonding technology alone.

SoIC Is One Layer Inside a Larger Package a die-stacking technology, not the whole assembled product FULL PACKAGE (interposer + memory + SoIC stack) HBM stack separate memory die SoIC stack dense direct-bonded dies I/O die interfaces, power delivery interposer / substrate — the package layer beneath all of these SoIC and an interposer-based package describe different levels of the same integration hierarchy

Stacking raises power density and can obstruct heat paths before the package is even finished, which is why thermal and test planning start before the stack is built, not after. Designers have to plan power delivery, thermal conduction, die order, clocking, and test access as part of the partitioning decision, and known-good-die screening reduces the value lost when a defective component gets joined — but bonding defects and failures that only show up after assembly remain a major contributor to the final yield and repair strategy.

"SoIC" means System on Integrated Chips in TSMC's advanced-packaging context, and a separate, older acronym — small-outline integrated circuit — means something unrelated in conventional component packaging. Writing "TSMC SoIC" resolves that ambiguity; beyond the name, a product claim should identify its actual bonding scheme and package arrangement rather than treating the acronym itself as proof of a particular pitch, stack depth, or performance gain.

Sources: [TSMC SoIC technology](https://3dfabric.tsmc.com/english/dedicatedFoundry/technology/SoIC.htm); [TSMC SoIC research publications](https://research.tsmc.com/page/off-chip-interconnect/1.html).

Read TSMC SoIC as TSMC's own chip-stacking technology family inside its 3DFabric portfolio — one layer within a larger package that also includes memory, interposers, and I/O dies — whose system-level benefit depends on partitioning, bonding quality, and thermal/test planning, not on the brand name alone.

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