power switch cell
# Power Switch Cell
Clock gating stops a block's logic from switching, but it doesn't stop that logic from leaking — at advanced nodes, leakage current can account for 30 to 50 percent of total chip power, and every one of those transistors keeps leaking whether or not the clock is toggling. Power gating is the only technique that actually drives leakage toward zero, and a power switch cell is the physical transistor that implements it: a large header or footer switch sitting between the real supply rail and a block's own virtual rail, connecting them during normal operation and disconnecting them entirely when the block sleeps.
Header and footer switches do the same job on opposite sides of the circuit, and header switches have become the more common choice in modern designs. A header switch is a large PMOS transistor placed between the real VDD and a virtual VDD rail that the block's own logic actually connects to — when the switch is on, virtual VDD tracks real VDD closely; when off, virtual VDD floats toward ground and every gate in the domain loses power. A footer switch does the mirror operation with an NMOS transistor between virtual ground and real ground. Both approaches achieve the same electrical isolation; header switches simply dominate modern practice, largely because PMOS switch sizing and leakage characteristics have worked out more favorably in most process libraries.
A single switch cell can't carry a whole block's current, which is why real implementations use arrays of switches with carefully controlled turn-on timing. One switch cell only has so much on-current capacity before its own IR drop across the switch becomes unacceptable, so production power-gating implementations place many switch cells in a grid or ring pattern across the domain, all driven by the same enable signal, collectively carrying the block's full current draw with the IR drop budget spread across the whole array. Turning every switch on simultaneously would dump a massive inrush current into the block's own decoupling capacitance all at once — a current spike that stresses the power network and can disturb neighboring circuits — so switches are often daisy-chained, turning on in a staggered sequence rather than all at once specifically to tame that inrush.
Power-up is a sequenced, multi-step process, not an instantaneous event, and retention registers and isolation cells both have defined roles in that sequence. The switch array turns on (potentially staggered), virtual VDD ramps from zero back up to full supply, isolation cells release once that supply has stabilized enough for the domain's outputs to be trusted again, and retention registers restore their saved state back into the now-repowered flip-flops before the block resumes normal operation — the exact save/restore and isolation sequencing both of those companion techniques are built around.
Isolation cells (3144) contain the electrical damage a powered-off domain's floating outputs would otherwise cause. Retention registers (610) preserve the specific state bits a block needs to resume cleanly. Power switch cells are the third piece completing the set — the actual physical mechanism that does the connecting and disconnecting all the other power-gating infrastructure exists to support.