more than moore

More than Moore (MtM) is the semiconductor design, process technology, and packaging paradigm that advances system-level performance, functional density, energy efficiency, and economic value through heterogeneous functional diversification rather than purely dimensional transistor scaling. Formally codified by the International Technology Roadmap for Semiconductors (ITRS) and continued under the IEEE International Roadmap for Devices and Systems (IRDS), More than Moore addresses the physical, thermodynamic, and economic ceilings of classic Dennard scaling and monolithic Moore's Law. While "More Moore" pursues the geometric miniaturization of digital CMOS logic—shrinking gate lengths and pitches from 28nm down through FinFET and Gate-All-Around (GAA) nanosheets to sub-2nm angstrom regimes—More than Moore integrates specialized, non-digital, and legacy technologies that do not benefit from transistor shrinking. These include radio frequency (RF) front-ends, high-voltage power management (BCD, GaN, SiC), micro-electro-mechanical systems (MEMS), analog sensors, and silicon photonics, unified into tightly coupled System-in-Package (SiP), 2.5D interposer (CoWoS, EMIB), and 3D wafer-to-wafer hybrid bonding architectures. By assigning each sub-function to its economically and physically optimal process node, More than Moore dismantles monolithic reticle and yield bottlenecks, serving as the foundational architectural pillar of modern artificial intelligence accelerators, high-performance computing, 5G/6G wireless networks, and autonomous automotive systems.

The shift toward More than Moore was forced by the simultaneous breakdown of Dennard scaling, interconnect RC delay limits, and the soaring economic penalties of monolithic defect yields. Historically, Robert Dennard's 1974 scaling theory dictated that as MOSFET dimensions shrank by a factor of κ (κ ≈ 1.4 per generation), transistor switching delay decreased by 1/κ while dynamic power density remained constant:

P = C_ox A V_dd^2 f + I_leak V_dd

By 2005, gate oxide thickness approached quantum mechanical tunneling limits (~1.2 nm), causing gate leakage current (I_leak) to spike exponentially. To prevent runaway thermal dissipation, supply voltages (V_dd) could no longer scale proportionally with feature size, stalling operating clock frequencies in the 3–5 GHz range (the "Power Wall"). Simultaneously, wire resistance exploded as interconnect cross-sectional dimensions shrank (R_wire = rho L / A ∝ kappa^2), causing interconnect RC propagation delay to dominate total gate delay:

tau_interconnect = R_wire C_wire ∝ L^2

Compounding these physical limits is the exponential economic penalty of monolithic silicon area described by Murphy's and Poisson's semiconductor yield models:

Y = e^-A · D_0 implies C_die = (C_wafer)/(N_dies × Y(A))

where A is die area and D₀ is defect density per unit area. In leading-edge 3nm and 2nm nodes, wafer manufacturing costs exceed 20,000 to 30,000, and fabricating a massive monolithic die approaching the optical lithography reticle limit (~858 mm²) results in catastrophic yield collapse. Partitioning a large monolithic SoC into specialized, smaller chiplets (e.g., four 150 mm² compute dies plus separate I/O and memory dies) multiplies net yield, avoids wafer defect write-offs, and cuts total silicon manufacturing cost by 30% to 50%. Furthermore, because advanced die-to-die packaging interconnects (such as UCIe and high-density silicon interposers) reduce channel parasitic capacitance from tens of picofarads down to femtofarads, interconnect energy per bit plummets:

E_bit = (1)/(2) C_channel V_dd^2 (E_bit < 0.5 pJ/bit in 2.5D vs. 5--10 pJ/bit across PCB traces)

The dual vectors of semiconductor technology evolution—More Moore and More than Moore—serve fundamentally complementary physical roles. More Moore is inward-facing: it scales digital computation, logic density, and algorithmic throughput within the mathematical realm of bits. More than Moore is outward-facing: it interfaces that digital core with the continuous analog, electromagnetic, optical, and physical phenomena of the real world. Integrating both vectors through advanced heterogeneous packaging creates systems that exceed the performance, cost, and energy envelope of any monolithic design:

In modern artificial intelligence supercomputing and electric mobility, More than Moore architectures break through monolithic performance bottlenecks. In generative AI accelerators (such as the NVIDIA Blackwell B200 and AMD Instinct MI300), training trillion-parameter large language models (LLMs) requires tens of terabytes of memory bandwidth and immense computational density. Monolithic integration cannot deliver this: a standard DRAM memory cell relies on deep trench or stacked cylindrical capacitors fabricated with high-temperature processing steps that would melt the copper interconnect metallization layers of a leading-edge logic die. More than Moore resolves this "Memory Wall" through 2.5D CoWoS and 3D TSV packaging, stacking eight to twelve high-bandwidth memory (HBM3e) DRAM dies vertically and placing them micrometers away from twin 4nm GPU compute dies on a passive silicon interposer. This architecture delivers over 8 TB/s of aggregate memory bandwidth at sub-picofarad capacitive loading, bypassing the high latency and energy drain of traditional PCB memory buses. In electric vehicle powertrain systems, an 800V traction inverter requires microcontrollers to compute field-oriented motor control algorithms while power stages switch hundreds of amperes at 800V. Monolithic integration is impossible because 800V transients would instantly vaporize 1V digital logic. By utilizing More than Moore heterogeneous SiP integration, automotive engineers mount wide-bandgap Silicon Carbide (SiC) power MOSFETs, 180nm BCD galvanic isolators and gate drivers, and 16nm automotive-grade MCUs into a compact power module, cutting parasitic inductance, slashing switching losses, and increasing driving range.

Five critical engineering pitfalls and physical failure modes threaten More than Moore heterogeneous integration. First, the Known Good Die (KGD) Compounding Trap: assembling multiple dies without pre-packaging verification results in catastrophic package scrap rates. If an advanced package combines eight chiplets each tested to 95% individual yield, the overall module yield collapses to (0.95)^8 pprox 66.3%, throwing away 33.7% of finished multi-thousand-dollar modules. Foundries must mandate comprehensive wafer-level probing, built-in self-test (BIST), and boundary scan architectures. Second, Thermomechanical Warpage and CTE Mismatch: silicon (CTE ≈ 2.6 ppm/°C), organic package substrates (CTE ≈ 15 ppm/°C), and copper micro-bumps (CTE ≈ 16.5 ppm/°C) expand at drastically different rates during solder reflow and operational thermal cycling. This differential expansion generates mechanical shear stress that cracks micro-bumps, tears underfill, and delaminates die interfaces. Third, Thermal Trapping in 3D Stacks: stacking high-power logic dies directly beneath temperature-sensitive DRAM accelerates DRAM capacitor leakage and forces frequent refresh cycles, degrading memory bandwidth. Thermal co-design requires placing high-power compute dies on the top of the stack, utilizing diamond heat spreaders, or inserting microfluidic cooling channels. Fourth, Die-to-Die Interconnect Latency and Congestion: partitioning tightly coupled algorithmic logic pipelines across physical die boundaries introduces serial transmission delays and clock domain crossing overheads that can erase chiplet parallelism benefits if interconnect standards (such as UCIe or BoW) are improperly configured. Fifth, Diagnostic Opacity and Test Inaccessibility: once dies are bonded onto silicon interposers with fine-pitch micro-bumps (<25 μm), physical probe cards cannot contact interior signals, requiring robust adherence to IEEE 1838 standard test access architectures for 3D stacked integrated circuits.

Read More than Moore not as a concession to the slowing of physical transistor scaling, but as the liberation of semiconductor architecture from the tyranny of the single substrate: it replaces the brute-force shrinking of homogeneous silicon with the deliberate orchestration of specialized physics, uniting logic, memory, power, RF, and optics into a coherent, high-yield system.