microprocessor 1971 four bit arithmetic unit decimal correction

# Build the Arithmetic Unit: Four-Bit Binary Addition With Decimal Correction

## 1. Make One Ripple-Carry Adder Serve the Accumulator

The Intel 4004 performs arithmetic through a four-bit ripple-carry adder connected to its four-bit accumulator, index registers, internal bus, and carry/link flip-flop. Each bit position adds one accumulator bit, one operand bit, and the carry arriving from the less-significant position. Its sum becomes the corresponding result bit; its carry advances to the next stage.

For bit position $i$,

$$S_i=A_i\oplus B_i\oplus C_i$$
$$C_{i+1}=A_iB_i+C_i(A_i\oplus B_i)$$

The least-significant stage receives the existing carry/link value when an ADD operation requests addition with carry. The final carry leaving bit 3 is stored back in that flip-flop. Because the four stages are connected in sequence, a carry produced at the low end must ripple through intermediate stages before the high-order result is settled. This saves the extra circuitry of a wider or more elaborate adder while matching the four-bit word chosen in Step 2.

Four Full-Adder Stages Pass Carry From Right to Left accumulator + selected operand + carry/link → new accumulator and carry/link FOUR-BIT RIPPLE-CARRY PATH BIT 3A3 + B3 + C3sum S3 BIT 2A2 + B2 + C2sum S2 BIT 1A1 + B1 + C1sum S1 BIT 0A0 + B0 + C0sum S0 C1C2C3 CARRY/LINK IN C4 S3 S2 S1 S0 → ACCUMULATOR · C4 → CARRY/LINK the same physical path supports ADD, increment, subtraction, and address work under different controls narrow arithmetic minimizes hardware; carry preserves information beyond four bits

## 2. Recognize That a Valid Binary Sum Can Be an Invalid Decimal Digit

The adder itself is binary. If it adds decimal digits 7 and 8, it produces $1111_2$, which is the binary value 15. But a single binary-coded-decimal digit may use only $0000_2$ through $1001_2$ for decimal 0 through 9. The patterns 1010 through 1111 are valid binary numbers but invalid decimal-digit codes.

The 4004 resolves this with a separate DAA instruction—Decimal Adjust Accumulator. According to the MCS-4 manual, DAA increments the accumulator by 6 when the carry/link is already 1 or when the accumulator contains a value greater than 9. Adding six skips the six unused four-bit patterns and produces the correct low decimal digit, with carry representing the next decimal position.

$$7+8=15=1111_2$$
$$1111_2+0110_2=1\,0101_2$$

The corrected accumulator is $0101_2$, decimal 5, and carry/link is 1: together they encode decimal 15. If the original binary addition already overflowed four bits, carry/link requests the same correction and remains the decimal carry even when the correction itself does not generate another overflow.

Decimal Adjust Converts a Binary Subtotal Into a BCD Digit example: decimal 7 + 8 becomes digit 5 with a decimal carry BINARY ADD0111+ 1000111115 BINARY · INVALID BCD DIGIT DAA TESTACC > 9or carry/link = 1ADD 0110 BCD RESULT1 | 0101carry | accumulatortens digit | ones digitDECIMAL 15 binary hardware stays general; a decoded correction step serves decimal arithmetic the correction is an explicit instruction, not an automatic property of every addition

## 3. Combine General Binary Hardware With Calculator-Specific Support

The arithmetic unit illustrates the architectural compromise at the center of the 4004. Its physical adder remains a general binary circuit, useful for arithmetic, counting, incrementing addresses, and other state transformations. Calculator-oriented decimal behavior is supplied by control and a dedicated adjustment operation rather than by replacing the core with a decimal-only adder.

This also clarifies the decoder's role from Step 4. An ADD opcode selects the accumulator, the addressed register, carry/link, and the adder path. A later DAA opcode selects the correction behavior, including the special conversion logic described in Intel's block-level documentation. The same gates and registers perform different work because stored instructions activate different control paths.

Step 5 has built the processor's computation path, but instructions still need a persistent source outside the CPU. Step 6 will place the program in a separate 4001 mask-programmed read-only-memory chip and contrast that stable instruction store directly with the refreshing, writable DRAM cell built in the 1968 series.

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