isolation cell
# Isolation Cell
Power gating a block only saves power if the rest of the chip can keep running normally while that block sits dark — and a powered-off block's own outputs don't just quietly disappear, they float to whatever undefined voltage the now-unpowered transistors happen to settle at. An isolation cell sits at every boundary between a gated domain and the always-on logic around it, clamping that floating output to a defined, safe value the moment the domain powers down, so the rest of the chip never sees the garbage a dead block would otherwise leak into it.
Floating outputs aren't just a logic-correctness problem — they're a direct electrical hazard to whatever receives them. A powered-off domain's output settling at some intermediate voltage, rather than a clean logic 0 or 1, drives the receiving gate's input into a region where both its PMOS and NMOS pull-paths can conduct simultaneously, pulling real short-circuit current that wastes power exactly where power-gating was supposed to save it. Worse, an unexpected intermediate voltage at the wrong node can trigger parasitic latch-up paths that exist dormant in every CMOS process. An isolation cell exists specifically to prevent both failure modes at once, by guaranteeing the signal crossing the domain boundary is always a clean, legal logic value, whether the source domain is powered or not.
Which value gets clamped depends on what the receiving logic actually needs, and that choice gets built into the cell type itself. Clamp-low isolation forces the output to logic 0 whenever isolation is asserted, implemented as the data signal ANDed with the inverted isolation control; clamp-high does the mirror operation with an OR gate, forcing logic 1 instead. Latch isolation takes a third approach, holding the last valid value the domain produced before power-down rather than forcing a fixed constant — useful when downstream logic needs a plausible-looking last-known-state rather than a hard-coded safe default. The isolation control signal itself has to assert before the power switches actually cut supply, and de-assert only after the domain is fully back up and stable, a sequencing requirement power-management verification checks explicitly rather than assumes.
UPF or CPF power-intent files, not the RTL itself, are where isolation requirements actually get specified, which is what lets synthesis and place-and-route insert these cells automatically rather than by hand. A power-intent file declares which domain boundaries need isolation, which clamp type each boundary needs, and which signal controls it — physical design tools then insert an isolation cell at every qualifying output port automatically during synthesis or place-and-route, typically placed on the always-on side of the boundary specifically so the cell itself never loses power even while the domain it's isolating sits dark. Power-aware verification checks the result against three separate criteria: every gated-domain output actually has an isolation cell, the isolation control signal sequences correctly relative to power switching, and the clamped value is functionally correct for whatever logic receives it.
Charge pump design (566) and LDO dropout (565) both generate or regulate the voltages a chip's power rails actually need. Isolation cells solve a different problem entirely — not generating power, but containing the electrical consequences of deliberately removing it from part of the chip, which is exactly the companion technique power gating needs to actually deliver its promised savings without corrupting everything connected to the block it turns off.