interconnect rc delay
Interconnect RC Delay is the signal propagation delay through on-chip metal wires caused by wire resistance (R) and parasitic capacitance (C) — which has surpassed transistor gate delay as the dominant performance limiter at advanced nodes, with the RC time constant increasing as metal cross-sections shrink despite improvements in conductor and dielectric materials.
The RC Delay Problem
- RC delay: $\tau = R \cdot C = \rho \frac{L}{A} \cdot \epsilon \frac{A_{cap}}{d}$
- As metal pitch scales: wire cross-section shrinks → R increases. Wire spacing shrinks → C increases.
- Double penalty: Both R and C get worse simultaneously.
- At 28nm: gate delay ~5 ps, interconnect delay ~20 ps — wires are 4x slower than transistors.
- At 3nm: gate delay ~1 ps, interconnect delay ~50+ ps — wires are 50x slower.
Resistance Scaling
- Copper resistivity increases dramatically at nanoscale due to:
- Grain boundary scattering: More grain boundaries per unit length in narrow wires.
- Surface scattering: Electrons scatter off wire surfaces (Fuchs-Sondheimer effect).
- Barrier/liner thickness: 2-3 nm TaN/Ta liner occupies 20-40% of wire cross section at M1 pitch < 30 nm.
- Cu bulk: 1.7 μΩ·cm → Cu at 20 nm width: ~5-8 μΩ·cm (3-5x increase).
Capacitance Scaling
- Wire-to-wire capacitance: $C \propto \epsilon_r \frac{H}{S}$ (H = wire height, S = spacing).
- Low-k dielectrics: SiO2 (k=4.0) → SiCOH (k=2.5-3.0) → Air gap (k=1.0).
- Further k reduction limited by mechanical and thermal requirements.
Solutions Being Deployed
| Approach | Target | Benefit |
|---|---|---|
| Alternative metals (Co, Ru, Mo) | Lowest metal levels | Thinner barriers → more conductor area |
| Air gap dielectrics | Tightest pitch layers | k=1.0 between wires |
| Backside power delivery (BSPDN) | Power/ground routing | Frees front-side for signal routing |
| Subtractive patterning (Ru, Mo) | Tightest pitches | Avoids damascene barrier limitations |
| Repeater insertion | Long signal paths | Break long RC lines into shorter segments |
Impact on Chip Architecture
- Chiplets: Avoid longest on-chip wires by splitting into smaller dies.
- 3D stacking: Vertical connections (TSV, hybrid bonding) shorter than horizontal wires.
- Near-memory compute: Minimize data movement distance to reduce interconnect bottleneck.
Interconnect RC delay is the fundamental performance bottleneck of modern semiconductor technology — solving it requires simultaneous innovation in conductor materials, dielectric materials, patterning approaches, and chip architecture, making BEOL engineering as critical as transistor design.