hmos 1978 quantify current matching and aspect ratio tradeoff

# Step 3 — Quantify the Current-Matching and Aspect-Ratio Tradeoff

## 1. The Inverter Voltage Transfer Constraint: Securing $V_{OL}$

In a depletion-load NMOS inverter, output logic levels and noise margins are determined not by complementary switching, but by a ratioed current fight between pull-down and pull-up transistors. In Step 1, we established that keeping supply voltage fixed at $V_{dd} = 5.0\ \text{V}$ while shrinking channel length escalates the internal electric field $E = V/L$. In Step 2, we showed how ion implantation decouples the depletion load’s threshold $V_{TD}$ from the enhancement switcher’s threshold $V_{TE}$. But making this co-scaled inverter functional requires balancing their drive currents across switching transitions.

Unlike CMOS—where either the PMOS or the NMOS transistor is completely turned off in steady state—an NMOS inverter with a depletion-mode load ($V_{GS,L} = 0$) operates as an active current source fighting an active pull-down switch. When the input voltage is high ($V_{in} = V_{OH} = 5.0\ \text{V}$), the pull-down transistor $Q_D$ turns ON to pull the output to logic low ($V_{out} = V_{OL}$). To maintain a valid TTL-compatible low level and a sufficient low noise margin ($NM_L = V_{IL} - V_{OL}$), the design must enforce:

$$V_{OL} \le 0.4\ \text{V}$$

At this steady-state low operating point:
* The pull-down enhancement device $Q_D$ operates in its linear (triode) region because $V_{DS,D} = V_{OL} = 0.4\ \text{V} \ll (V_{in} - V_{TE})$:

$$I_{D} \approx \beta_D \left[(V_{in} - V_{TE}) V_{OL} - \frac{1}{2} V_{OL}^2\right] \approx \beta_D (V_{dd} - V_{TE}) V_{OL}$$

* The pull-up depletion load $Q_L$ has $V_{DS,L} = V_{dd} - V_{OL} \approx 4.6\ \text{V} > |V_{TD}|$. Thus, $Q_L$ operates in saturation, delivering its full saturation current:

$$I_{L} = \frac{1}{2} \beta_L |V_{TD}|^2$$

where $\beta = \mu C_{ox} (W/L)$ represents the transconductance parameter of each transistor.

Depletion-Load NMOS Inverter: Current Matching at VOL ratioed logic constraint: linear pull-down current balancing saturated depletion load current CIRCUIT TOPOLOGY (RATIOED LOGIC) Vdd = 5.0 V QL (Dep) VGS = 0 Vout = VOL ≤ 0.4V QD (Enh) Vin = 5V Vin GND (0 V) Current Balance Condition: ID,linear(VOL) = IL,sat → Sets Geometry Ratio I-V CHARACTERISTIC & OPERATING POINT Vout IDS IL (Depletion Load Saturation) ID (Vin = 5V) VOL = 0.35 V The Geometric Ratio Formula: KR = (W/L)D / (W/L)L ≈ |VTD|2 / [2(Vdd - VTE) VOL] For VTD = -2.5V, VTE = 0.8V, VOL = 0.35V → KR ≈ 3.5 to 4.0 THE RATIOED SIZING MANDATE ✓ The Pull-Down Must Overpower the Load: To achieve VOL ≤ 0.4V, the pull-down transconductance βD must be 4× larger than βL ✓ The Aspect Ratio Penalty: Making the load 4× weaker required making its channel 4× longer than minimum lithography Before ion implantation, this 4:1 aspect-ratio requirement squandered silicon area on serpentine load transistors.

## 2. The Aspect Ratio Tradeoff: Pre-HMOS Serpentine Loads vs. HMOS Sizing

Equating pull-down linear current to pull-up saturation current yields the required aspect ratio $K_R$:

$$\frac{\beta_D}{\beta_L} = \frac{(W/L)_D}{(W/L)_L} \approx \frac{|V_{TD}|^2}{2 (V_{dd} - V_{TE}) V_{OL}}$$

For typical operating parameters ($V_{dd} = 5.0\ \text{V}$, $V_{TE} = 0.8\ \text{V}$, $V_{TD} = -2.5\ \text{V}$, $V_{OL} = 0.35\ \text{V}$), this ratio simplifies to:

$$K_R = \frac{(W/L)_D}{(W/L)_L} \approx \frac{(-2.5)^2}{2(5.0 - 0.8)(0.35)} = \frac{6.25}{2.94} \approx 2.1$$

When taking into account the body effect (as $V_{out}$ approaches $V_{OL}$, the depletion load’s source-to-substrate reverse bias shifts $V_{TD}$ via $\Delta V_T = \gamma(\sqrt{2\phi_F + V_{out}} - \sqrt{2\phi_F})$), the required aspect ratio climbs to $K_R \approx 3.5\text{ to }4.0$.

Physical Layout Comparison: Pre-HMOS vs. HMOS Inverter how precision ion implantation rescued silicon area from bloated serpentine load channels PRE-HMOS NMOS (6 µm LITHOGRAPHY) QD Switcher W=6 µm, L=6 µm (W/L) = 1.0 QL Serpentine Load (L = 24 µm!) W/L = 6/24 = 0.25 (KR = 4:1) Area Penalty & Sluggish Pull-Up: • Load transistor occupies 4× more die area than switcher • Massive gate capacitance slows rising propagation delay tPLH • Inverter pair footprint: ~360 µm² HMOS-I (3.5 µm + DUAL IMPLANT) QD Switcher W=7, L=3.5 µm (W/L) = 2.0 QL Compact Load W=3.5, L=7 µm W/L = 0.5 (KR = 4:1) As⁺ Implant Tuning VTD = -2.5V Stable 4× Area Reduction & 2× Speed: • Independent VTD tuning eliminates serpentine channel waste • Load current matches switcher without bloated parasitic capacitance ✓ Inverter pair footprint: ~85 µm² (> 4× denser!) The Architectural Payoff of Step 3: By engineering VTD via ion implantation, HMOS preserved the 4:1 transconductance ratio while shrinking the load channel length from 24 µm to 7 µm.

## 3. Place This Step in the Project's Own Lineage

Step 3 provides the quantitative circuit bridge that links process physics to microarchitecture:
1. The Ratioed Sizing Cost Unveiled: Step 1 showed why constant-voltage scaling pushed fields to dangerous levels, and Step 2 introduced ion implantation as the process lever to decouple threshold voltages. Step 3 delivers the circuit-level proof: without independent implant control of $V_{TD}$, maintaining $V_{OL} \le 0.4\ \text{V}$ required a $4:1$ aspect-ratio mismatch ($K_R \ge 4$), forcing fabs to lay out massive $L_L = 24\ \mu\text{m}$ load resistors that squandered die area.
2. The Density Dividend: By precisely adjusting the depletion implant dose ($D \approx 1\times 10^{12}\ \text{cm}^{-2}$), HMOS designers locked $V_{TD}$ at $-2.5\ \text{V}$. This allowed the load channel length to shrink from $24\ \mu\text{m}$ to $7\ \mu\text{m}$, slashing the inverter pair’s silicon area by $4\times$ while halving switching propagation delay ($t_{PLH}$).
3. Setting Up Gate Oxide Thinning: Having reclaimed layout density and current matching through aspect-ratio optimization, circuit designers faced their next performance bottleneck: drive current ($I_{on} \propto C_{ox} (W/L)$). In Step 4, we examine HMOS’s second scaling lever: thinning the gate oxide ($t_{ox}$) from $100\ \text{nm}$ down to $70\ \text{nm}$ to boost drive current without shrinking $L$ further, and confronting the resulting dielectric breakdown limits.

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