gate poly etch process flow

# Gate Poly Etch Process Flow

Gate Poly Etch Process Flow describes the sequence connecting pattern preparation, removal and verification.

## Follow the transitions

Each box marks a manufacturing purpose, not an executable recipe. Some integrations combine steps or move strip and clean operations. Endpoint, where used, must be qualified against feature clearing and underlayer loss.

## Integration context

This is a conventional patterned polysilicon gate over a gate dielectric. BARC is an optional bottom antireflective coating; its opening is separate from native-oxide breakthrough. Main removal and a selective landing step must preserve the thin gate dielectric and avoid silicon recess.

## What to verify

Check gate CD, residual poly, gate dielectric loss and electrical damage.

The illustrated sequence omits tool settings and integration-specific auxiliary steps. For AlCu, corrosion-control treatment must be coordinated with resist removal and atmospheric exposure. For gate and spacer modules, preserving a thin dielectric or exposed silicon is part of the clearing window, not an afterthought.

## Related terminology

gate poly etch process flow, poly etch, gate etch, poly gate etch. Short abbreviations are local process vocabulary and can have other meanings; use the full module name when searching.

## Source and scope

[Fabrication and etch resources](https://www.cleanroom.byu.edu/processes). The diagram is an original teaching schematic. Layer choices and process families describe an example rather than a universal manufacturing recipe.