dual work function
High-k metal gate (HKMG) integration, replacement metal gate (RMG / gate-last) processing, and dual work function metal (WFM) engineering constitute the foundational materials revolution that sustained Moore's law scaling below the 45nm node. When conventional silicon dioxide (SiO_2) and silicon oxynitride (SiON) gate dielectrics were thinned below 1.2 nm, quantum mechanical direct tunneling current exploded exponentially, creating unmanageable standby power dissipation and thermal dissipation crises in mobile and server processors. Furthermore, legacy poly-silicon gate electrodes suffered from poly-silicon gate depletion, adding 0.3--0.5 nm of parasitic capacitance thickness (Delta t_inv) that degraded gate electrostatic control. Transitioning to hafnium-based high-k dielectrics (HfO_2, k ≈ 20--25) enabled physical dielectric thickness to increase while scaling Equivalent Oxide Thickness (EOT) below 0.8 nm, suppressing gate leakage by more than three orders of magnitude. Replacing poly-silicon with atomic layer deposited (ALD) work function metals eliminated poly depletion entirely, while gate-last RMG architectures preserved pristine metal work functions from high-temperature source/drain activation anneals.
Hafnium oxide high-k gate dielectrics scale Equivalent Oxide Thickness below sub-nanometer limits while slashing direct tunneling leakage. In nanoscale MOS gate stacks, Equivalent Oxide Thickness (EOT) quantifies the physical thickness of a hypothetical SiO_2 dielectric that would yield the identical gate capacitance per unit area (C_ox). The total gate dielectric stack consists of a native or chemically grown interfacial SiO_x layer (t_IL ≈ 0.4--0.6 nm) capped by an atomic layer deposited hafnium dioxide (HfO_2) layer (t_high-k ≈ 1.5--2.5 nm, k_high-k ≈ 22):
EOT = t_IL + t_high-k ( (k_SiO2)/(k_high-k) ) = t_IL + t_high-k ( (3.9)/(22) ) ≈ 0.7--0.9 nm.
Because the direct quantum mechanical tunneling leakage current density (J_tunnel) decreases exponentially with physical barrier thickness (J_tunnel ∝ exp[-2 d sqrt(2 m^* Phi_B)/hbar]), increasing the physical dielectric thickness from 1.0 nm (SiO_2) to 2.5 nm (IL + HfO_2) reduces gate dielectric leakage by more than 1000× at identical gate operating voltages (|V_GS| = 0.75--1.0V).
Replacement metal gate architectures prevent high-temperature thermal degradation of work function metals and preserve gate oxide integrity. In legacy Gate-First integration schemes, metal gates and high-k dielectrics were deposited before high-temperature source/drain dopant activation spike anneals (1000^°C to 1050^°C), which caused metal diffusion, oxygen vacancy generation, and severe Fermi level pinning that locked threshold voltages to undesirable mid-gap states. The Replacement Metal Gate (RMG / Gate-Last) process solves this by using a sacrificial poly-silicon dummy gate during source/drain implant and activation. After depositing inter-layer dielectric (ILD0) and planarizing with chemical mechanical polishing (CMP) down to the dummy gate tops, the sacrificial poly-silicon is selectively wet-etched with hot tetramethylammonium hydroxide (TMAH) or ammonium hydroxide (NH_4OH). High-k dielectrics and work function metals are subsequently deposited inside the pristine gate trenches under a low thermal budget (< 450^°C), preserving pristine band-edge effective work functions and eliminating metal-induced interface defects.
| Gate Integration Architecture | Gate Dielectric Stack | Equivalent Oxide Thickness (EOT) | Gate Electrode Material | Poly Depletion Penalty (Delta t_inv) | Maximum Thermal Exposure | Target Technology Generation |
|---|---|---|---|---|---|---|
| Poly-Si / SiO_2 (Legacy) | Thermal SiO_2 / SiON | > 1.4 nm | In-situ doped poly-silicon | High (0.3--0.5 nm) | 1050^°C (S/D spike anneal) | 90nm, 65nm Planar |
| Gate-First HKMG | SiON + HfSiO_x / HfO_2 | 1.0--1.2 nm | Capped metal + poly-silicon | Eliminated (0 nm) | 1000^°C (Severe V_th shift risk) | 45nm, 32nm Planar |
| Gate-Last RMG (High-k First) | SiO_x + HfO_2 | 0.8--1.0 nm | ALD TiAl / TiN + W fill | Eliminated (0 nm) | 1000^°C (Dielectric only) | 28nm, 20nm Planar |
| Gate-Last RMG (High-k Last) | Ozone SiO_x + ALD HfO_2 | < 0.8 nm | ALD TiAlC / TiN + Co / W | Eliminated (0 nm) | < 450^°C (Full thermal protection) | 16nm to 3nm FinFET |
| 3D GAA Nanosheet RMG | Dipole SiO_x + HfO_2 | < 0.65 nm | Multi-layer ALD nano-WFM | Eliminated (0 nm) | < 400^°C (Extreme thermal control) | 2nm, A16 GAA & CFET |
Dual band-edge work function metals and interfacial dipole engineering deliver precise multi-threshold voltage tuning across CMOS standard cell libraries. In modern CMOS technologies with undoped FinFET or nanosheet channels, the transistor threshold voltage (V_th) is established by the flatband voltage (V_FB = Phi_m,eff - Phi_s), which is directly controlled by the metal gate effective work function (Phi_m,eff):
V_th ≈ ( Phi_m,eff - Phi_s ) + 2 psi_B + (sqrt(2 q epsilon_Si N_sub (2 psi_B)))/(C_ox).
To achieve symmetric, low threshold voltages (|V_th| ≈ 0.2--0.3V) without chemical channel dopants that induce random dopant fluctuations (RDF), foundries deposit band-edge work function metals: titanium aluminum (TiAl, TiAlC, Phi_eff ≈ 4.0--4.2 eV) for NMOS, and titanium nitride (TiN, TaN, Phi_eff ≈ 5.0--5.2 eV) for PMOS. Furthermore, nanometer-thin lanthanum oxide (La_2O_3) or aluminum oxide (Al_2O_3) dipole capping layers induce electrostatic dipole moments at the HfO_2/SiO_x interface, providing continuous 100--200 mV threshold voltage modulation to synthesize Standard-V_th (SVT), Low-V_th (LVT), and Super-Low-V_th (SLVT) library flavors.
Delivering peak transistor transconductance and minimum static leakage across advanced FinFET and GAA nanosheet architectures requires evaluating gate electrostatics through a high-k-metal-gate-hkmg-and-replacement-metal-gate lens. By uniting interfacial oxide thickness scaling, ALD HfO_2 high-k deposition, gate-last dummy poly removal, band-edge dual work function metal deposition, and interfacial dipole threshold engineering, foundry integration teams maximize channel carrier velocity. Mastering HKMG device physics ensures that high-performance AI processors, energy-efficient mobile SoCs, and ultra-dense SRAM memory arrays operate with maximum drive current, low supply voltages, and multi-decade dielectric breakdown reliability.