DAC gain error

# DAC Gain Error

DAC gain error is the difference between the actual and ideal transfer slope after offset has been removed. A converter can have small steps and still deliver the wrong voltage span. Gain error tells you how far that span is stretched or compressed.

## Read the slope, then the intercept

For an ideal unipolar N-bit voltage DAC with unity output gain, V(D) = VREF × D / 2ᴺ. The largest code is 2ᴺ − 1, so its ideal output is one ideal LSB below VREF. Use the transfer equation in the device datasheet for bipolar, current-output, or internally amplified converters.

The teal line illustrates positive gain error after offset removal. A negative error would reduce the slope. The illustration exaggerates the difference; a real DAC has discrete codes rather than a continuous line.

Model the settled response as V(D) = b + mD + r(D). Here b is offset, m is the fitted slope, and r(D) is the remaining deviation from that line. Relative gain error is (m / mideal − 1) × 100%. Some datasheets express it as a percentage of full-scale range; follow their test codes and definition.

Full-scale error includes other contributions if offset has not been removed. Integral nonlinearity describes residual curvature relative to a specified reference line. Differential nonlinearity describes individual step-size error. A two-point adjustment cannot remove either kind of nonlinearity.

## A calculated example

Take an illustrative 12-bit DAC with a 4.096 V reference. Its ideal slope is 1 mV/code. Suppose the actual slope is 1.002 mV/code and offset is +3 mV. The gain error is +0.2%, or +2000 ppm. At code 2000, the output is 2.007 V: 4 mV from slope error and 3 mV from offset. At code 4000, slope error alone becomes 8 mV.

The two measurements give m = (3.6102 − 0.4038) / (3600 − 400) = 0.001002 V/code and b = 0.003 V. To request a voltage Vtarget, use Dcommand = round((Vtarget − b) / m) and check that the result is within the available code range. For 2.000 V this gives code 1993, predicting 1.999986 V in this linear example. That 14 µV difference is rounding, not a guaranteed accuracy specification.

## Where the span error comes from

The output span depends on the reference, conversion network and output stage. Reference tolerance, resistor-ratio error, buffer gain, loading and temperature can change the system slope. Intrinsic DAC gain error and end-to-end signal-chain gain error are different measurement boundaries: determine whether the datasheet excludes external reference error before combining budgets.

## Calibrate under the conditions you will use

1. Stabilize supplies, reference, temperature and output load. Allow the output to settle before measuring.
2. Choose two well-separated codes within the specified linear operating region. Avoid rail clipping or zero-code deadband; use the manufacturer's recommended calibration points.
3. Measure both outputs with equipment whose uncertainty is suitable for the required accuracy. Fit slope and intercept from those readings.
4. Apply the inverse equation and clamp only after checking whether the requested target is reachable. Software cannot recover an output beyond the physical span.
5. Sweep additional codes to inspect residual error. Repeat across relevant temperatures and loads when drift matters.

Calibration removes the fitted slope and offset at the calibration conditions. It does not eliminate INL, noise, drift after calibration, reference instability, output settling error or measurement uncertainty. Near code limits, correction may consume headroom; budget that loss before choosing the required output range.

## Engineering takeaway

Resolution counts the steps; gain accuracy sets their overall scale. Measure a span, remove offset, and inspect the residual across the range. That sequence prevents a single full-scale reading from disguising which error actually needs correction.

## Sources and further reading

• [Analog Devices — Open-Loop Calibration Techniques for Digital-to-Analog Converters](https://www.analog.com/en/resources/analog-dialogue/articles/open-loop-calibration-techniques.html): linear transfer model and calibration context.
• [Analog Devices — How to Successfully Calibrate an Open-Loop DAC Signal Chain](https://www.analog.com/en/resources/technical-articles/how-to-successfully-calibrate-an-open-loop-dac-signal-chain.html): signal-chain calibration and temperature considerations.

Original illustrations and numerical example; values describe a teaching model, not a specific product.