chiplet ecosystem
The Chiplet Ecosystem and Die-to-Die Standards is the industry framework for creating interoperable disaggregated semiconductor systems where dies from different vendors, foundries, and technology nodes can be assembled into a single package using standardized interfaces — moving beyond proprietary multi-die integrations toward an open ecosystem analogous to how PCIe standardized component interconnects, enabling customers to mix and match best-of-breed dies without being locked to a single vendor's full-stack solution.
Chiplet Motivation
- Monolithic die yield falls rapidly with die area → economic limit ~600mm² at leading node.
- Moore's law slowing → smaller nodes not always better for all functions (RF, analog, I/O benefit less).
- Heterogeneous integration: Mix leading-node logic + mature-node I/O + specialized dies → optimal cost/performance.
- Time to market: Reuse validated IP chiplets → shorter development cycle than full monolithic SoC.
Proprietary vs Open Chiplet Interfaces
- Proprietary (before standards):
- AMD Infinity Fabric: Connects CPU + GPU + memory chiplets (Instinct MI300X).
- Intel EMIB: Embedded multi-die interconnect bridge (Ponte Vecchio).
- NVIDIA NVLink Chip2Chip: Used for Grace-Hopper superchip.
- Open standards: Enable multi-vendor chiplet marketplaces.
UCIe (Universal Chiplet Interconnect Express)
- Launched 2022 by AMD, ARM, Intel, Qualcomm, Samsung, TSMC, Meta, Google.
- Physical layer: Defines bump pitch, signaling, link training → multi-vendor interoperability.
- Protocol layer: Maps PCIe 6.0 or CXL 3.0 over UCIe physical → retains software stack compatibility.
| Tier | Bump Pitch | BW/mm | Power/Gbps |
|---|---|---|---|
| Advanced (2.5D) | 25 µm | 16 Tbps/mm | 0.5 pJ/bit |
| Standard (package) | 100 µm | 2 Tbps/mm | 2 pJ/bit |
BSII / OpenHBI / BoW
- BoW (Bunch of Wires): Open Alliance standard → simple parallel wires, no protocol overhead → ultra-low latency.
- OpenHBI (Hybrid Bond Interconnect): JEDEC standard for hybrid-bonded die-to-die → < 1 µm pitch.
- AIF (Advanced Interface Bus): Intel-led standard for 3D heterogeneous chiplet stacking.
Chiplet Marketplaces
- TSMC CoWoS Design Infrastructure: Provides chiplet IP validated for CoWoS assembly.
- Intel Foundry Services (IFS) Chiplet Program: Third-party chiplets on Intel packages.
- ASE Group Chiplet Design Center: Backend assembly services for multi-vendor chiplet systems.
- Ayar Labs / Teramount: Optical I/O chiplets → photonic chiplets in package.
Supply Chain and KGD (Known-Good Die)
- Chiplet assembly risk: One bad die ruins entire package → need KGD (pre-tested, guaranteed good dies).
- KGD testing: Bare die test at wafer level → challenge: fine-pitch probing, thermal management.
- Burn-in of bare die: Stress screen before assembly → KGD qualification.
- Rework: Failed assembled unit → some packages allow rework (remove bad chiplet), most do not.
Chiplet Disaggregation Examples
| Product | Chiplet Split | Nodes |
|---|---|---|
| AMD Epyc Genoa | 12 core chiplets + 1 I/O die | 5nm core + 6nm I/O |
| AMD MI300X | 8 compute chiplets + 4 active bridges | 5nm |
| Intel Meteor Lake | CPU + GPU + SoC + I/O tiles | 4nm + 5nm + 6nm + Intel 7 |
| Apple M3 Ultra | 2× M3 Max dies via die-to-die | 3nm |
The chiplet ecosystem and die-to-die standards are the supply chain infrastructure for the next generation of semiconductor economics — by enabling companies to assemble best-in-class dies from different foundries and vendors using UCIe-standardized interfaces, the chiplet paradigm promises to do for semiconductor systems what containerization did for global shipping: create a standardized modular ecosystem where specialized component suppliers can address diverse end-markets without each customer requiring a full custom vertical integration, potentially breaking the winner-take-all dynamics of leading-edge foundry competition by making process technology just one dimension of system optimization.