chiplet design integration
Chiplet Architecture and Disaggregated Design is the semiconductor design paradigm that decomposes a monolithic system-on-chip into multiple smaller dies (chiplets) fabricated independently and interconnected through advanced packaging — enabling mix-and-match combinations of process nodes, IP blocks, and foundries within a single package to overcome the yield, cost, and design complexity limits of monolithic scaling.
Why Chiplets
A monolithic 800 mm² die at 3 nm has punishingly low yield — one defect kills the entire chip. Splitting the same design into four 200 mm² chiplets dramatically improves yield (defects only kill one chiplet, which is cheaper to replace). Additionally, not all functional blocks benefit from the latest process node — I/O, analog, and memory controllers work well at mature nodes (12-28 nm), while compute logic benefits from 3-5 nm.
Chiplet Interconnect Standards
- UCIe (Universal Chiplet Interconnect Express): The industry-standard die-to-die interface. Defines physical (bump pitch, PHY), protocol (PCIe, CXL), and software layers. Supports 32-64 GT/s per lane, 167-1317 Gbps/mm² bandwidth density depending on packaging technology (standard vs. advanced).
- BoW (Bunch of Wires): OCP (Open Compute) standard for chiplet I/O. Simplified PHY for cost-sensitive applications.
- Proprietary: AMD Infinity Fabric (EPYC/Ryzen chiplets), Intel EMIB/Foveros link, Apple proprietary (M1 Ultra die-to-die).
Packaging Technologies for Chiplets
| Technology | Bump Pitch | Bandwidth | Example |
|---|---|---|---|
| Organic substrate (standard) | 100-150 μm | 40-100 GB/s | AMD EPYC Rome |
| EMIB (Embedded Multi-die Interconnect Bridge) | 45-55 μm | 100-200 GB/s | Intel Ponte Vecchio |
| CoWoS (Chip on Wafer on Substrate) | 25-45 μm | 200-900 GB/s | NVIDIA H100/B200 |
| Foveros (3D stacking) | 25-36 μm | 1+ TB/s | Intel Meteor Lake |
| SoIC (System on Integrated Chips) | <10 μm | >2 TB/s | TSMC future |
Design Methodology Changes
Chiplet design shifts complexity from silicon to packaging and system integration:
- Known Good Die (KGD): Each chiplet must be fully tested before integration — defective chiplets are discarded before the expensive packaging step.
- Thermal Co-Design: Chiplets stacked vertically create thermal challenges — the top die's heat must pass through the bottom die. Active cooling channels and thermal interface engineering become critical.
- System-Level Verification: Traditional SoC verification tools must extend to multi-die systems with different clock domains, power domains, and process technologies.
Industry Adoption
- AMD EPYC: 8 compute chiplets (CCD, 5 nm) + 1 I/O die (IOD, 6 nm). The first high-volume commercial chiplet product.
- NVIDIA B200: 2 compute dies + HBM stacks on CoWoS. 208B transistors in the package.
- Intel Ponte Vecchio: 47 tiles from 5 process nodes, connected via EMIB and Foveros.
Chiplet Architecture is the semiconductor industry's answer to the economic and physical limits of monolithic scaling — decomposing the problem of building ever-larger chips into a modular, yield-optimized integration challenge that enables silicon capabilities impossible with any single die.