channel length modulation

Channel length modulation is the reason a transistor in saturation is not actually a perfect current source, no matter how the textbook equation first presents it. Raise the drain voltage on a MOSFET that is already saturated and the drain current still creeps upward — not because the device entered a new operating region, but because the region of the channel actually doing the work of conduction is physically shrinking underneath the fixed gate.

The Channel Shrinks While the Gate Stays Put pinch-off moves toward the source as drain voltage rises At V_DS = V_DSAT Channel runs full length, source to drain Pinch-off sits right at the drain edge At V_DS >> V_DSAT Depletion region widens near the drain Pinch-off retreats toward the source A shorter channel means lower resistance for the same overdrive So current keeps rising with V_DS, even though the device is "saturated."

The physical picture starts from where saturation itself comes from. In a MOSFET's triode region the inverted channel runs unbroken from source to drain; raising drain voltage past the saturation point (V_DS = V_GS − V_TH) pinches the channel off right at the drain edge, and in the simplest model the device then behaves as an ideal current source, independent of V_DS entirely. Real devices do not stop there: pushing V_DS further above that point widens the depletion region near the drain, and the point where the channel actually pinches off retreats from the drain back toward the source. The electrically active channel length shrinks by some ΔL, and resistance falls roughly in proportion — so drain current rises, gently, with drain voltage, instead of staying flat.

The standard long-channel equation patches this in as a single linear correction term, and the parameter λ is the whole story. The textbook saturation current equation multiplies the ideal, V_DS-independent result by (1 + λV_DS), where λ is an empirical channel-length-modulation parameter extracted per process node and per device length. λ is not a universal constant — it scales roughly as 1/L, because ΔL itself depends mostly on voltage and doping, not on the drawn channel length, so the same absolute ΔL is a much larger fractional change in a short device than a long one. This is precisely why channel-length modulation is a bigger problem, not a smaller one, as process nodes keep shrinking L.

Ideal vs. Real Saturation the slope that shows up as finite output resistance Ideal model (λ = 0) Current flat vs. V_DS Output resistance: infinite Real device Current rises with V_DS r_o = 1 / (λ·I_D) — finite Gain is capped by r_o, and λ scales roughly as 1/L Shrinking nodes make this worse — cascoding is the standard fix.
I_D vs. V_DS: the Slope That Shouldn't Be There the ideal curve is flat past saturation — the real curve never stops climbing V_DS I_D triode V_DSAT ideal (λ=0): I_D flat, r_o = ∞ real device: I_D rises, r_o finite slope = 1/r_o = λ·I_D pinch-off begins This slope — not visible anywhere in the idealized square-law equation — is what r_o = 1/(λI_D) actually measures

Output resistance is where channel-length modulation stops being a second-order correction and becomes a first-order design limit. The finite slope of the saturation I-V curve defines a small-signal output resistance, r_o = 1/(λI_D) — not infinite, as the ideal current-source picture implies, but a real, finite number that directly caps the voltage gain available from a single transistor. An amplifier's intrinsic gain is proportional to g_m·r_o; since r_o shrinks as λ grows and as bias current grows, the same channel-length modulation that is a rounding error for a digital logic gate is often the single dominant limit on how much gain an analog designer can extract from one device.

This is why analog and digital design treat the same physical effect with opposite levels of concern. A digital gate cares about on-current and switching speed, where a few percent of current drift with V_DS barely matters against the much larger swing between on and off. An analog gain stage built from the shortest, fastest transistors a process offers runs directly into the 1/L scaling of λ — which is exactly why high-gain analog building blocks (current mirrors, cascode stages, operational transconductance amplifiers) deliberately use longer-than-minimum channel lengths, trading some speed and area for the r_o a short, fast digital-style device simply cannot provide.

Cascoding is the standard circuit-level answer to a physical effect that cannot be designed out of the transistor itself. Stacking a second transistor on top of the first shields the bottom device's drain from large V_DS swings, holding it near its own saturation edge regardless of what the output node does — which multiplies the effective output resistance by roughly the stacked device's own intrinsic gain. The device-physics limit does not go away; the circuit topology simply stops exposing the sensitive node to the voltage swing that triggers it.

QuantityIdeal (long-channel, λ=0)Real device
I_D in saturationConstant vs. V_DSRises linearly with V_DS
Output resistance r_oInfinite1/(λI_D), finite
λ vs. channel length LNot modeledScales roughly as 1/L
Intrinsic gain g_m·r_oUnboundedCapped by λ, falls as L shrinks
Mitigation—Longer L, cascode topology

Channel length modulation is the device-physics fine print behind a circuit-level fact every analog designer learns early: gain is not free, and a transistor's own channel does not hold still just because the gate said saturation was reached. The same shrinking that makes logic faster and denser makes this correction larger, which is why the most basic MOSFET equation in any textbook carries a term for it at all.

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