capacitor over bit line

Capacitor-under-bit-line is a choice about which of two cell components gets built first, on top of the access transistor, and which one gets built last — and that ordering decision, as mundane as it sounds, directly determines whether a DRAM process can reach the storage capacitor with a short, direct contact or has to route around an entire bit-line layer sitting in the way.

The ordering question exists because one of these two structures is, by necessity, far taller and more topologically complex than the other. A DRAM storage capacitor has to hold enough charge to survive sensing against the bit line's own parasitic capacitance, discussed elsewhere in this series, while occupying a cell footprint that keeps shrinking every process generation — the only way to keep capacitance up as footprint shrinks is to build the capacitor tall, as a stacked cylinder or a deep trench, rather than flat. The bit line, by contrast, is comparatively simple: a planar conductor that just needs to make a clean, low-resistance contact down to the transistor's drain. Whichever structure is built second has to either route cleanly around whatever the first structure left behind, or be short enough not to need to.

Capacitor-over-bit-line architecture builds the bit line first, directly on the transistor, then builds the tall storage capacitor stacked on top of it with its own direct contact down through the bit-line layer to the transistor's storage node. This ordering avoids making the storage capacitor's own contact route around or through an already-built bit line, since the capacitor's contact goes straight down before the bit line's own routing geometry can get in the way at that specific location; it does mean the bit line sits at a lower, more cramped layer, and the stacked capacitor above it inherits whatever height constraints the manufacturing stack allows for a structure built later in the process.

Capacitor-under-bit-line architecture reverses that order: the storage capacitor is built first, directly on the transistor, and the bit line is routed above it afterward. This was historically the simpler integration path when storage capacitors were still comparatively flat and planar, since the bit line could be laid down cleanly over a low structure without needing to navigate around significant height. As cell scaling pushed capacitors toward tall stacked or cylindrical shapes to preserve enough charge storage in an ever-shrinking footprint, building the bit line over that same tall structure became progressively more awkward — the bit-line contact down to the transistor's other diffusion node had to either tolerate routing past the capacitor's increasing height, or the capacitor itself had to be kept shorter than ideal to accommodate the bit line above it.

This is why capacitor-over-bit-line became the dominant architecture as DRAM scaling pushed capacitor aspect ratios ever higher, while capacitor-under-bit-line remains associated with earlier, flatter-capacitor generations. Once the storage capacitor needed real vertical room to grow — stacking additional cylinder layers or deepening a trench — building it last, with an unobstructed straight shot upward and a direct contact straight down to the transistor, became the path of least resistance. The bit line, needing nothing more than a clean lateral routing layer, tolerates sitting below the capacitor far better than the capacitor tolerates being squeezed to accommodate a bit line already in its way.

Seen as an actual cross-section rather than a text comparison, the build-order difference is just as direct: COB stacks a tall, unobstructed capacitor on a thin bit-line layer; CUB caps the capacitor's height before the bit line is even routed.

Capacitor-under-bit-line and its counterpart are a reminder that a memory cell's final electrical performance is decided as much by construction sequence as by any single component's own design — the same storage capacitor behaves very differently depending on whether it is built with room to grow or squeezed in under a layer that was already there first. As this series' DRAM-architecture entries keep showing, from folded bit-line's noise rejection to sub-word-line's flat timing, DRAM scaling has repeatedly been solved not by a cleverer single component but by deciding, carefully, in what order and in what shape the array's structures get built.