5nm-process

A process generation, not a five-nanometer gate. A 5nm process is a foundry-defined manufacturing platform for dense integrated circuits. Its name identifies a generation of transistors, wiring, design rules, libraries, and qualified manufacturing steps. Gate length, contacted gate pitch, metal pitch, and SRAM cell area remain different physical quantities. Comparing vendors therefore requires measured circuit characteristics and a specified design, rather than treating the label as a dimensional standard.

FinFETs with a larger role for EUV. Commercial 5nm-class platforms continued the FinFET architecture while extending lithography and integration. Extreme ultraviolet exposures could replace some complicated immersion-lithography patterning sequences on selected layers. Other layers still used deep ultraviolet tools. EUV did not remove deposition, etch, alignment, metrology, or defect-control requirements; the complete process flow determined whether dense patterns became reliable electrical circuits.

TSMC N5 as a historical example. TSMC reported that N5 entered volume production in the second quarter of 2020. Its annual report also described N4 as an extension of the N5 family. These are company-specific milestones: an N5 derivative and another supplier’s 5nm offering need not share pitches, devices, yield, or reusable IP. A platform name should accompany any product or manufacturing-date claim.

Useful density differs from advertised density. A chip combines logic, SRAM, analog, interfaces, clocking, power distribution, and physical whitespace. Each component scales differently. Routing congestion and power limits may prevent a design from using the smallest available cells everywhere. A density comparison is most informative when it states the cell libraries, SRAM contribution, utilization, and whether the result represents a small test structure or an assembled product.

What changes for a designer. Migration requires a qualified process design kit, timing and power models, extraction rules, and physical verification. Reusing an architecture does not make the layout portable. Designers trade area and speed against leakage, voltage, reliability, manufacturing cost, and package constraints. The practical benefit is a better implementation of a particular workload within those constraints, rather than a universal improvement guaranteed by the node number.

Sources and further reading. [TSMC 2020 annual report](https://investor.tsmc.com/static/annualReports/2020/english/ebook/files/basic-html/page7.html); [TSMC advanced smartphone technologies](https://www.tsmc.com/english/dedicatedFoundry/technology/platform_smartphone_tech_advancedTech).

Read 5nm process as a foundry platform whose value depends on circuits, manufacturing quality, and system requirements.