4f2-dram

A cell-area expression, not a process-node name. 4F² DRAM describes a memory-cell layout occupying approximately four times the square of a reference feature dimension F. In a simplified regular array, a 2F-by-2F footprint has that area. The convention concerns cell geometry; it does not mean a four-nanometer process. Comparisons must use the same definition of F and identify which structures are included in the quoted cell area.

Vertical access transistors help compact the footprint. Conventional one-transistor, one-capacitor DRAM must fit an access device, storage capacitor, word line, and bit line into a repeatable cell arrangement. Standing the access channel vertically can reduce the area it consumes in the wafer plane. A surrounding or vertical gate can improve channel control, but contacts, isolation, and conductor placement must still fit within the proposed pitch.

Published work includes integration demonstrations. A 2025 IEEE VLSI paper describes 4F² DRAM integration with a vertical-gate cell transistor and peri-under-cell architecture. SK hynix’s associated roadmap discussion presents vertical-gate 4F² as a future scaling platform. These disclosures establish a research and integration direction. They should not be read as evidence that every DRAM vendor has shipped a qualified commercial product using that architecture.

Nominal cell shrink is not equal to die shrink. At fixed F, a 4F² footprint is two thirds the area of a 6F² footprint. That arithmetic describes the idealized cell comparison, not a guaranteed one-third reduction in finished memory-die area. Sense amplifiers, decoders, redundancy, peripheral circuits, contacts, capacitor requirements, and array efficiency can change the practical result. Yield and the cost of added process steps also affect useful bit density.

Retention and interference still determine usability. A compact cell must retain enough signal for reliable sensing while controlling leakage and disturbance. Vertical devices introduce their own electrostatic, parasitic, and fabrication considerations. Dense arrays require verification across temperature, variation, refresh conditions, and access patterns. The relevant product comparison is reliable bits per cost and energy, rather than cell footprint alone or an assumption that a vertical transistor automatically creates multilayer 3D DRAM.

Sources and further reading. [IEEE 2025 integration paper](https://ieeexplore.ieee.org/document/11075066/); [SK hynix VLSI 2025 roadmap](https://news.skhynix.com/en/sk-hynix-presents-future-dram-technology-roadmap-at-ieee-vlsi-2025/).

Read 4F² DRAM as a compact DRAM cell-layout target that requires demonstrated integration, retention, and manufacturing economics.