2nm-process
A generation associated with nanosheet logic. A 2nm process is an advanced logic platform defined by a semiconductor manufacturer. Leading examples use gate-all-around nanosheet transistors, but the node label itself is neither a measured channel length nor a universal specification. The relevant platform includes front-end devices, contacts, interconnect layers, libraries, design rules, reliability limits, and manufacturing controls needed to build complete integrated circuits.
Why the gate surrounds the channel. As channels shorten, the drain can influence the potential barrier that the gate is intended to control. Wrapping a gate around a thin semiconductor sheet improves electrostatic control compared with less fully surrounded geometries. Stacking sheets supplies useful drive current within a compact footprint. Sheet thickness, width, number, spacing, and contact geometry still create tradeoffs between performance, capacitance, leakage, and manufacturability.
Two documented company milestones. TSMC reports that N2 entered volume production in the fourth quarter of 2025. Samsung’s January 2026 results state that its foundry business commenced mass production of first-generation 2nm products during the fourth quarter of 2025. These statements describe each company’s own technology and reporting criteria. They do not imply common design rules, interchangeable customer IP, or equal manufacturing scale.
Backside power is a separate integration choice. A nanosheet device does not inherently require power delivery from the wafer’s backside. Transistor architecture and power-network architecture are distinct decisions, even when a supplier combines them in a later platform. Claims about backside contacts, buried rails, or routing benefits should name the specific process variant. Otherwise an advantage of one derivative can be incorrectly assigned to an entire node family.
Qualification turns a structure into a platform. A convincing transistor demonstration is only one step toward reliable products. Designers need characterized libraries, memory compilers, interface IP, extraction models, and tools that support the actual process rules. Manufacturing must control variation and defects across wafers and lots. Useful comparisons include routed circuit performance, SRAM behavior, reliability, yield learning, and the cost of delivering a functional packaged chip.
Sources and further reading. [TSMC logic technology](https://www.tsmc.com/english/dedicatedFoundry/technology/logic/l_2nm); [Samsung Q4 2025 results](https://news.samsungsemiconductor.com/global/samsung-electronics-announces-fourth-quarter-and-fy-2025-results/).
Read 2nm process as a vendor-qualified logic platform whose nanosheet devices must be evaluated together with wiring and design support.