28nm-process

A 28 nm process is a manufacturing-platform generation rather than a universal transistor dimension. Its devices, wiring pitches, gate stack, libraries, and qualification rules depend on the supplier and process variant. Bulk CMOS and fully depleted silicon-on-insulator can both carry a 28 nm label while using different substrate structures and design methods. The name therefore needs a manufacturer and platform context.

TSMC announced 28 nm volume production in October 2011. The announcement is a dated manufacturing milestone, distinct from an earlier research demonstration or customer design tape-out. It places the generation within the expansion of advanced foundry platforms. Other suppliers and variants followed their own development and qualification schedules.

28 nm process Conceptual comparison; not a manufacturing specification or scale drawing Historical anchor TSMC volume production October 2011 Platform choices Bulk CMOS / FD-SOI Gate stacks and device options Design evaluation Logic + SRAM + analog + I/O Routing and qualification matter A generation name identifies a platform family; actual dimensions and operating limits require its process specification.

Gate-stack choices and leakage targets divide the generation into different offerings. A high-k and metal-gate stack changes gate coupling and electrode behavior, while the transistor geometry still determines channel control. Low-power and performance-oriented libraries make additional trade-offs. A node label alone cannot establish a device’s threshold options, operating voltage, or standby consumption.

Interconnect and memory remain major contributors to usable density. Logic cells, SRAM arrays, analog blocks, and I/O circuits scale differently. Routing congestion and power distribution can consume area that a transistor-only estimate misses. The meaningful comparison is a placed and routed design or a clearly defined test structure using the actual design rules.

Process selection follows the complete product requirement. Performance, energy, manufacturing yield, available IP, and lifecycle requirements all influence the choice. A later numerical node is not automatically the best implementation for every circuit. The 28 nm generation illustrates how a qualified platform can retain value through specialization and a mature design ecosystem.

Sources and further reading. [TSMC 28 nm volume-production announcement, October 2011](https://pr.tsmc.com/schinese/news/1689).

Read 28 nm process as a family of qualified manufacturing platforms whose usefulness depends on device options, design support, and product requirements.

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